EMAC32 - Pin Description
Frozen Content
The following pin description is for the EMAC32 when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Table 1. EMAC32 pin description.| Name | Type | Polarity / Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| WBS_CLK_I | I | Rise | External (system) clock signal |
| WBS_RST_I | I | High | External (system) reset |
| CLK_MD | I | Rise | External clock signal used for the PHY Register Interface. This signal must be less than 1MHz in frequency. |
| Host Processor Interface Signals | |||
| WBS_STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| WBS_CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| WBS_ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| WBS_ADR_I | I | 5 | Address bus, used to select an internal register of the device for writing to/reading from |
| WBS_DAT_O | O | 32 | Data to be sent to host processor |
| WBS_DAT_I | I | 32 | Data received from host processor |
| WBS_WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| WBS_INT_O | O | High | Interrupt signal. An interrupt can be generated either from the Receiver or Transmitter. The corresponding enable bits for these interrupts can be found in the RX_INT and TX_INT registers respectively. The following interrupts can be generated by the Receiver:
The following interrupts can be generated by the Transmitter:
|
| Memory Interface Signals | |||
| WBM_STB_O | O | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| WBM_CYC_O | O | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| WBM_ACK_I | I | High | Standard Wishbone device acknowledge signal. When this signal goes high, the connected Wishbone slave device has finished execution of the requested action and the current bus cycle is terminated |
| WBM_ADR_O | O | 32 | Standard Wishbone Address bus. Used to select an address in the connected Wishbone slave device for writing to/reading from |
| WBM_DAT_I | I | 32 | Data received from the connected Wishbone Slave device |
| WBM_DAT_O | O | 32 | Data to be sent to the connected Wishbone Slave device |
| WBM_SEL_O | O | 4/High | Select output, used to determine where data is placed on the WBS_DAT_O line during a Write cycle and from where on the WBS_DAT_I line data is accessed during a Read cycle. For the EMAC32, only 32 bit data transfers are supported, meaning that all the lines go high during a Read/Write cycle |
| WBM_WE_O | O | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| Media Independent Interface (MII) Interface Signals | |||
| PHY_TXD | O | 4 | Data to be transmitted to the PHY |
| PHY_TXEN | O | High | Transmit data enable. This signal goes High when transmitting data to the PHY |
| PHY_TXC | I | Rise | Transmit clock. Used to clock the data that is transmitted to the PHY |
| PHY_RXD | I | 4 | Data received from the PHY |
| PHY_RXDV | I | High | Receive Data Valid signal. This signal goes High if data on the PHY_RXD bus is valid |
| PHY_RXER | I | High | Receive Error signal. This signal goes High if the PHY detects a receive error |
| PHY_RXC | I | Rise | Receive clock. Used to clock the data received from the PHY into the Controller |
| PHY_COL | I | High | Used to flag the detection of a collision |
| PHY_CRS | I | High | Carrier Sense signal. This signal goes High if the carrier is detected at the network side of the PHY |
| PHY_RESETB | O | Low | Resets the PHY. This signal is the logical NOT of the WBS_RST_I signal. Therefore resetting the EMAC32 will cause a reset of the connected PHY device. Note that the connected PHY device can also be reset by writing a '1' to the rst bit of the PHY Command register (PHY_CMD.31) |
| PHY Register Interface Signals | |||
| PHY_MDC | O | Rise | PHY register clock |
| PHY_MDOE | O | Low | Enable signal for the address/data transmitted from the PHY_MDO pin |
| PHY_MDO | O | 1 | Address/Data transmitted to PHY registers |
| PHY_MDI | I | 1 | Data received from PHY registers |