EMAC32 - Interrupts

For both the Receiver and Transmitter an interrupt register is available to enable different interrupt sources – RX_INT and TX_INT respectively. For normal use, there is no need for any software intervention while transmitting or receiving packets. Just make the transmit packets available by copying these to the Transmit Buffer and updating the TX_INPUT register. The received packets are available in the Receive Buffer for further processing. Only in exceptional cases are the interrupts useful, for example when there are errors in the Receiver or Transmitter.

In such cases, enable the required interrupt sources in the RX_INT and/or TX_INT register. If an interrupt occurs, the interrupt flag can be read in the corresponding Status register for the Receiver (RX_STATUS) or Transmitter (TX_STATUS).

Interrupts are cleared by writing a '1' to the corresponding interrupt flag bit in the Status register. Note however that this does not clear the cause of the interrupt. Some interrupt causes are automatically cleared (e.g. receiver lack-of-space) or need to be cleared by setting a bit in the RX_CMD or TX_CMD register (e.g. receiver overflow).