Custom Logic Tutorial - Processing the Design

Now that the design has been fully captured and targeted to our daughter board FPGA device, we can go ahead and process the design – ultimately creating the required FPGA programming file with which to program the target device.

1. Ensure that your Desktop NanoBoard is connected to your PC and powered on.
    
2. Ensure that the Devices view is the active view within Altium Designer and that the Live option is enabled and the Connected indicator is Green.
    

3. In the associated 'Process Flow' for the physical device, click on the Program FPGA button - the last stage in the flow. The design will be compiled, synthesized and the vendor tools invoked. Ultimately the FPGA programming file will be generated and downloaded, via JTAG, to the physical device on the daughter board.
    
   

   Figure 1. Starting the programming process.

Once the design has been downloaded, the text underneath the physical device's icon in the Devices view will change from Reset to Programmed. On the hardware side, the 'Program' LED on the daughter board will be lit (Green), confirming the design has been loaded into the physical device.

Note: The C-to-Hardware Compiler takes the exported C functions and generates intermediate HDL files (containing the hardware circuit definitions), which are used by the Synthesizer, along with intermediate HDL files for the top-level schematic and Custom Instrument, in the creation of the top-level EDIF netlist – suitable for the Vendor Place & Route tools. For this tutorial, we have used the default Compiler Netlist setting (VHDL). This can be changed to Verilog on the FPGA - General page of the Preferences dialog (DXP » Preferences), should you prefer.

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