Configurable Generic Library

Altium Designer Winter 09 heralds the arrival of a new integrated library of configurable generic FPGA logic components – FPGA Configurable Generic.IntLib. The aim of this library is to provide many of the logic components found in the existing FPGA Generic.IntLib, but delivered as single configurable components, enabling you to design in a far more efficient and streamlined manner.

The FPGA Configurable Generic.IntLib can be found in the \Library\Fpga folder of your Altium Designer installation, and is included as part of the default installed libraries for your convenience.

The following sections provide a brief overview of the components available.

DIVIDER - Configurable Divider (Available from Release 10)
MULTIPLIER - Configurable Multiplier (Available from Release 10)
BARRIER - Configurable Barrier (Available from Release 10)
BUS_JS - Configurable Bus Joiner/Splitter
GATE - Configurable Generic Gate
BUF & INV - Configurable Buffer/Inverter
REGISTER - Configurable Register
MEMORY - Configurable Memory
FIFO - Configurable FIFO buffer

DIVIDER - Configurable Divider

The configurable divider allows the user to calculate the quotient and remainder of an unsigned integer division.
The user can configure a number of options, including:

• Type (Division, Modulo or both)
• The width of the Nominator and Denominator ports
• The number of bits to calculate per cycle (the total number of cycles is equal to the "divider width" / "number of bits per cycle")
• Bus or wire inputs and outputs
• Rising or Falling edge clocks
• Select to register the output

The following ports are created:

• A Nominator inport port (N)
• A Demoninator input port (D)
• An optional Quotient output port (Q)
• An optional Remainder output port (R)
• An optional START port (if divider is not combinatorial)
• An optional DONE port (if divider is not combinatorial)
• Optional CLK & RST ports (if divider is not combinatorial)

START shall be asserted when the inputs are valid. START is only sensed if a previous division is not in progress. DONE is asserted only during the clock cycle when the outputs become valid.

Figure 1. Example Divider components with configuration dialog.

MULTIPLIER - Configurable Multiplier

The configurable multiplier allows the user to multiply two signed integers. The multiplier is combinatorial.
The user can configure a number of options, including:

• The width of the input ports
• Bus or wire inputs and outputs
• Rising or Falling edge clocks
• Select to register the output

The following ports are created:

• Two input ports (I0 and I1)
• One output port (O)
• An optional START port (if outputs are registered)
• Optional CLK & RST ports (if outputs are registered)

START shall be asserted when the inputs are valid.

Figure 2. Example Multiplier components with configuration dialog.

BARRIER - Configurable Barrier

The configurable barrier allows the user to configure a barrier synchronization method.

Behavior:

• basically the barrier is and AND port with memory
• the output is raised when all inputs are high, or have been high since the output was raised previously
• output is asserted at the same time the last input becomes high (during the same clock cycle, thus combinatorial)
• output de-asserted after the first rising clock signal when output is asserted

The user can configure a number of options, including:

• The number of inputs (I0, I1, ...)
• Whether the inputs are inverted or not
• Bus or wire inputs
• Output (O) asserted at rising or falling edge of clock
• Enable optional inverted output (NO)

Figure 3. Example Barrier components with configuration dialog.

BUS_JS - Configurable Bus Joiner/Splitter

The new configurable bus joiner/splitter allows signals of arbitrary signal widths to be joined to form a single bus. Conversely, a single bus can be split into individual signals, with widths that the user specifies.

Figure 4. Example BUS_JS components.

GATE - Configurable Generic Gate

The new configurable gate allows the user to configure their gate in any way they wish. The gate type can be changed on the fly; the number of inputs can be changed. The user can specify which inputs they want to invert. Also, the user can select to register the output.

Figure 5. Example simple GATEs.

There is also an option to perform bitwise operation on bus inputs. Simply select Bus for the Input Type and bitwise operation on the bus inputs will be performed.

Figure 6. Example uber fancy GATE.

BUF & INV - Configurable Buffer/Inverter

The configurable buffer and inverter allows the user to specify arbitrary input sizes. Three output options are available: Normal, Inverted or Normal/Inverted.

Figure 7. Example BUF components.

REGISTER - Configurable Register

The configurable register allows the user to configure a number of options, including:

• Choosing between D Flip-Flop and Transparent Latch.

• Input signal widths can be specified.

• Set and reset mode can be selected to be synchronous or asynchronous.

• Negative clock edge

• Clock enable.

Figure 8. Example REGISTER components.

MEMORY - Configurable Memory

The configurable memory allows the user to configure a number of options, including:

• Memory Width and Depth

• ROM or RAM with either a single or dual port interface

• Rising or Falling edge clocks

• May utilize distributed memory or block RAM

• Initialization from file

Figure 9. Example MEMORY component with configuration dialog.

FIFO - Configurable FIFO buffer

The configurable FIFO allows the user to configure a number of options, including:

• Width and Depth

• Rising or Falling edge clocks

• May utilize distributed memory or block RAM

• Option status pins

Figure 10. Example FIFO component with configuration dialog.