Frozen Content
Modified by Admin on Sep 13, 2017
Figure 1 below describes the dataflow between the two main Finite State Machines in the Receiver and Transmitter blocks.
Figure 1. Main dataflow between Receiver and Transmitter.
Figures 2 and 3 illustrate state machine diagrams for the Receiver and Transmitter respectively.
Figure 2. Receiver Finite State Machine diagram.
Figure 3. Transmitter Finite State Machine diagram.