CANB_W - Architectural Overview

The following sections detail the architectural elements that comprise the CANB_W Controller.

FIFO Control Unit (FifoCtrl) with Receiver FIFO (RAM)

The Receive FIFO stores received and accepted messages from the CAN-bus. The Receive Buffer register represents a 13-byte window of the Receive FIFO which itself has a total length of 64 bytes.

With the help of this FIFO, the CPU is able to process one message while other messages are being received. The Receive FIFO is implemented using dual port RAM.

The FIFO Control Unit controls the operation of the Receive FIFO which may implemented either as Receive FIFO or as distributed RAM. Within the FifoCtrl block, there is a Message Counter (MC) that informs about the number of messages stored in the Receive FIFO and a Receive Buffer Start Address register (RBSA), that informs about the position of the Receive Buffer register window within the Receive FIFO.

In order to shift the RBSA register to the next message position, all message bytes of the current message must be read from the Receive FIFO and the Release Receive Buffer bit subsequently set in the Command Register (CMR.2).

Figure 1. FIFO Control Unit (FifoCtrl) with Receive FIFO (RAM).

Transmit Buffer (TB)

The Transmit Buffer stores a complete message for transmission over the CAN network. The buffer is 13 bytes long. In order to transmit the message, the CPU writes the message into this buffer and sets the Transmission Request bit (CMR.0) or Self Reception Request bit (CMR.4) in the Command Register.

Figure 2. Transmit Buffer (TB).

Acceptance Filter (AF)

The Acceptance Filter compares the received message identifier with the contents of the Acceptance Filter registers and determines whether the message should be accepted and written into the Receive FIFO or not. Within the Acceptance Filter block there are four Acceptance Code registers (ACR0 – ACR3) and four Acceptance Mask registers (AMR0 – AMR3).

Functionality of this block mainly depends on the Acceptance Filter Mode selected in the Mode register (single or dual) and whether the frame format of the message being received is standard or extended.

The Acceptance Filter is controlled by the Bit Stream Control Receiver (RecBSC).

Figure 3. Acceptance Filter (AF).

Bit Timing Logic (BTL)

The Bit Timing Logic block monitors the CAN-bus line and handles the bus line-related bit timing. It is synchronized to the bit stream on the CAN-bus on a 'recessive-to-dominant' bus line transition at the beginning of a message (hard synchronization) and re-synchronized on further transitions during the reception of a message (soft synchronization).

The BTL also provides programmable time segments to compensate for the propagation delay times and phase shifts (e.g. due to oscillator drifts) and to define the sample point and the number of samples to be taken within a bit time. To this end, there are two programmable registers – BTR0 and BTR1.

The BTL also derives the CLK_OUT signal, by dividing the system clock signal (CLK_I) by the number stored in the Clock Divider register (CDR). The CLK_OUT signal can be used as the clock signal for a processor. While entering Sleep Mode, the CLK_OUT signal continues until at least 15 bit times have passed. This allows a host processor clocked by this signal to safely enter its own standby mode before the CLK_OUT signal goes Low.

Within the BTL block, there are also programmable registers responsible for output and input mode control and logic that controls waking up the CAN Controller from Sleep Mode.

Figure 4. Bit Timing Logic (BTL).

CAN Interface (CANIN)

The CAN Interface is an interface between the CAN-bus line transceiver and the CAN Controller.

Figure 5. CAN Interface (CANIN).

CPU Interface Logic (IL)

The CPU Interface Logic controls write and read access to the CAN Controller registers from the CPU.

Figure 6. CPU Interface Logic (IL).

Error Management Logic (EML)

The Error Management Logic is responsible for the error confinement of the transfer-layer modules. It receives error announcements from the Receiver and then informs the Interrupt and Status Control Unit (ISC) about error statistics.

The main components of the EML are:

• Receive Error Counter (REC)

• Transmit Error Counter (TEC)

• Error Warning Limit register (EWL).

Figure 7. Error Management Logic.

Interrupt & Status Control (ISC)

The Interrupt & Status Control unit is responsible for interrupt generation, establishing requested CAN Controller status and interpreting commands in the Command register (CMR).

This block controls all other CAN Controller blocks.

Figure 8. Interrupt & Status Control.

Bit Stream Control Receiver (RecBSC)

The Receiver is the main component in the CAN Controller structure. It functions as a Bit Stream Processor. The BSC Receiver monitors the CAN-bus line and controls message reception. This block is responsible for performing BOSCH CAN 2.0B protocol. It performs bus arbitration, CRC calculation and checking, error detection, error signaling and bit destuffing.

The BSC Receiver controls the data stream between the Receiver FIFO and the Bit Timing Logic block. It also derives control signals for the Acceptance Filter, Fifo Control Unit, Transmit Buffer and Error Management Logic.

Figure 9. Bit Stream Control Receiver.

Bit Stream Control Transmitter (TrBSC)

The main function of the Transmitter Unit is, as its name suggests, message transmission. It also:

• forms frames

• sends acknowledgements, Error and Overload Flags

• performs bit-stuffing.

The Transmitter controls the data stream between the Transmit Buffer and the Bit Timing Logic block.

Figure 10. Bit Stream Control Transmitter.