BT656 - Transmitted Pixel Data

The value that is sent to the FIFO is constructed using the value in the RGB or GREY register, in accordance with the color mode defined in the MODE register (MODE4..2). The value is stored in an intermediate register – FIFO_IN. Table 1 summarizes the pixel data sent for each of the color modes supported by the Controller.

Once the pixel value is ready, it is written to the FIFO. The process then repeats, with the next pixel converted after the required X-scaling is observed, until the end of the current line in the video stream.

From FIFO to External Memory

As soon as pixel data has been written to, and made available in, the FIFO, it is written to the external memory. The address in memory where the next pixel is to be written is calculated based on the content of the BPL and VBPL registers – the latter being used only if scaling/zooming has been applied.

The external memory will be written to starting from the address defined by the START register. Pixels will continue to be written to memory until the memory size defined by the SIZE register has been reached. The BT656 Controller will never write to a memory address outside of the 'memory window' defined by the START and SIZE registers.

Before data is sent out to external memory on the Controller's WBM_DAT_O line, its endianness needs to be correct. For 32-bit color modes this is already the case. For 16- and 8-bit color modes, this essentially means swapping the data so that the MSB becomes the LSB.

An intermediate buffer register – DSWAP – is used to receive the 32-bit pixel value from the FIFO. The bytes of this register are then placed on the WBM_DAT_O line in accordance with the color mode used, as summarized in Table 2.