BT656 - Pin Description

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Modified by Admin on Sep 13, 2017

The following pin description is for the BT656 component when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.

Table 1. BT656 pin description.

Name	Type	Polarity/ Bus size	Description
Control Signals
CLK_I	I	Rise	External (system) clock signal
RST_I	I	High	External (system) reset
Host Processor Interface Signals
WBS_STB_I	I	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
WBS_CYC_I	I	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
WBS_ACK_O	O	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated
WBS_ADR_I	I	3	Address bus, used to select an internal register of the device for writing to/reading from
WBS_DAT_O	O	32	Data to be sent to host processor
WBS_DAT_I	I	32	Data received from host processor
WBS_SEL_I	I	4/High	Select input, used to determine where data is placed on the WBS_DAT_O line during a Read cycle and from where on the WBS_DAT_I line data is accessed during a Write cycle. For the BT656 Controller, only 32-bit data transfers are supported, meaning that all the lines go High during a Read/Write cycle.
WBS_WE_I	I	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
INT_O	O	2/High	Interrupt output lines. Two interrupts are sent to the connected processor on this 2-bit bus: bit 0 = Frame Interrupt. Goes High when the next frame is being written to the external memory. bit 1 = Line Interrupt. Goes High when the next line is being written to the external memory.
External Video Memory Interface Signals
WBM_STB_O	O	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
WBM_CYC_O	O	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers
WBM_ACK_I	I	High	Standard Wishbone device acknowledge signal. When this signal goes high, the connected Wishbone slave device has finished execution of the requested action and the current bus cycle is terminated
WBM_ADR_O	O	32	Standard Wishbone Address bus. Used to select an address in the connected Wishbone slave device for writing to
WBM_DAT_O	O	32	Data to be sent to the connected Wishbone Slave device
WBM_SEL_O	O	4/High	Select output, used to determine where data is placed on the WBM_DAT_O line during a Write cycle. For the BT656 Controller, only 32-bit data transfers are supported, meaning that all the lines go High during a Write cycle
WBM_WE_O	O	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
Video Data Input Signals
vid_data	I	8	ITU-R BT.656-compliant video data stream received from the connected Video Decoder device.
pclk	I	Rise	Pixel clock, used to clock the video data stream. The frequency of this clock is fixed at 27MHz.
vblk	I	High	Video blanking signal. When this signal goes High, the video data stream is not converted. This signal is sampled at byte 4 of the embedded sync data (EAV code) in the video data stream.