Automatic FPGA-PCB Linking - Configuring the FPGA Component Schematic Sheet
Whether the PCB project already exists or is being newly created, the relationship between the FPGA project and its corresponding component in the PCB project has to be managed in some way. This is achieved using a dedicated, auto-generated schematic sheet, referred to as the 'Main Sheet' and configured on the fourth page of the FPGA To PCB Project Wizard (Figure 1).
Figure 1. Configuration options for the schematic 'Main Sheet'.
This schematic sheet will be created with the component symbol placed for the FPGA device targeted in the constraint file (Figure 2). The Wizard allows you to determine where and by what name, the schematic is created.
Figure 2. Example auto-generated schematic sheet for a Xilinx Spartan-3 device (XC3S1500-4FG676C).
By default, the schematic will be named using the chosen designator for the FPGA component (e.g. FPGA_U1_Auto.SchDoc) and will be stored in the same location as the FPGA project.
Each used pin on the component symbol is linked to a port entry in the constraint file by signal (net label/port) name. The names for nets in the PCB project are therefore required to be the same as those in the FPGA project.
Once linked, any changes made to the source documents of either PCB or FPGA project can be passed on, ensuring that the two projects remain synchronized.
The Use Standard Sheet Size Where Possible option, when enabled, directs the Wizard to attempt to use a standard schematic sheet size, where possible, to encompass the component symbol(s) and related ports for the FPGA device. You also have the option of specifying the default measurement units used for the sheet – Metric or Imperial.
Should you wish to connect power pins of the device via dedicated power ports, ensure that the corresponding option for this is enabled on this page of the Wizard.
Use the Unused I/O Pins region of the page to determine how any unused I/O pins on the component are handled. You have the ability to control the treatment of various categories of I/O pin types individually:
- Input-only pins
- VREF pins
- Special Function pins and
- all other unused I/O pins.
The pins can be handled in one of the following ways:
| Tie to single port | – | Tie all unused pins in the category to a single port (which will also appear on the parent sheet symbol (if applicable) on the sheet above) |
| Tie to individual ports | – | Tie all unused pins in the category to their own, individual ports (which will also appear on the parent sheet symbol (if applicable) on the sheet above) |
| Tie to ports by IO bank | – | Tie all unused VREF pins to a port on a bank by bank basis (which will also appear on the parent sheet symbol (if applicable) on the sheet above) |
| Add No ERC directive | – | Add a No ERC directive to an unused pin, so that it is not included as part of error checking when the design is compiled |
| Ignore | – | Do nothing with an unused pin |
Note: For VREF pins, when the Tie to single port or Tie to ports by IO bank options are selected, you are given the additional option of whether or not to connect via Power Ports.