Altera Place and Route Tools Configuration
The place and route tools are all accessed and configured from the Build stage of the Process Flow associated to the target physical device in the Devices view. To enable and display the Process Flow when the target device is an Altera FPGA you must:
- Have the appropriate Altera vendor tools installed – either the full tool suite or the freely downloadable version available from the Altera website – and
- Your design must be configured for a valid Altera target architecture. This is done by including a suitable device constraint in a project constraint file, which belongs to a current project configuration (Project » Configuration Manager).
Build Options
The Build process allows interface with Altera tools and produces the device program files such as the Raw Binary Files (.rbf) for downloading into your target FPGA device. By clicking on the down arrow, a list of individual steps used to complete the Build process can be found (Figure 1).
Figure 1. Constituent stages of the Build process.
Click the Options icon () adjacent to each stage to configure that feature. Errors or design rules that are not allowed for your target architecture or in the design will be picked up at each stage of the Build process. The location in the design and the error or warning is logged in a report file, accessed by clicking on the appropriate Report icon ().
For advanced users who want more control over the options passed to the Altera tools, each stage in the Build process is linked to a single script file – DefaultScript_Quartus.Txt – located in the \System folder of the installation. Be aware that this script is defaulted to standard optimization – any changes should be carefully applied in consultation with the Altera Introduction to Quartus II Manual. Individual Build stages are described in the following sections.
Translate Design
This stage creates a Quartus TCL (TCLQ) script, settings, and project (Quartus) files that are used by all the subsequent steps in the Build process. The TCL (TCLQ) script links the files FPGA_HexMultiplier_constraints.tcl and FPGA_HexMultiplier_macros.tcl generated from the Synthesis process flow. The TCLQ file is then executed with the Quartus II Shell (Quartus_sh) using the -t switch.
The Altera project can be opened in Quartus if required.
Map Design To FPGA
This stage creates the Altera project database and map.eqn file by running the Quartus II Analysis & Synthesis (Quartus_Map) tool. It links all design files and performs technology mapping using the Quartus II TCL (TCLQ) script file.
Place and Route
This stage runs the Quartus II Fitter (Quartus_Fit) tool and Quartus TCL (TCLQ) script file to place and route the design for the target FPGA. It uses the .map, .eqn and other files generated from the Map Design to FPGA process.
Timing Analysis
This stage runs the Quartus II Timing Analyzer (Quartus_Tan) tool to analyze the speed and performance of the implemented logic for the target FPGA. Analysis options can be configure by clicking on the Options icon.
Make Bit File
This process runs the Quartus II Assembler (Quartus_Asm) tool to generate the Altera device programmable and configuration files, such as Hexadecimal (Intel-Format) Output Files (.hexout), Raw Binary Files (.rbf), Jam™ Files (.jam), Jam Byte-Code Files (.jbc) and Serial Vector Format Files (.svf), for downloading to the chip.