32-bit VGA Controllers - Host to Controller Communications

Communications between a 32-bit host processor and a 32-bit VGA Controller are carried out over a standard Wishbone bus interface. The following sections detail the communication cycles involved, where applicable, between host and Controller for writing to/reading from accessible internal registers and, in the case of the VGA32 Controller, the active color look-up table.

Writing to an Internal Register

Data is written from the host processor to an internal register in the VGA Controller, in accordance with the standard Wishbone data transfer handshaking protocol.
 

 
The actual 24-bit address sent out from the processor on its IO_ADR_O line is constructed as follows:

VGA Controller Base Address + (Internal Register Address & "00")

The base address for the VGA Controller is specified as part of the peripheral's definition when adding it as a slave to the Wishbone Interconnect. For example, if the base address entered for the device is 100000h (mapping it to address FF10_0000h in the processor's address space), and you want to write to the Horizontal Timing Register (HTIM) with address 0000000010b, the value entered on the processor's IO_ADR_O line would be:

100000h + 008h = 100008h

The following sections detail the write operation which, in each case, occurs on the rising edge of the CLK_I input.

All Writable Registers (except CTRL)

When writing to an internal register, bits 11..2 of the io_ADR_I line are used to address the register. The write operation can be summarized as follows:

• The host presents the required 24-bit address based on the register to be written on its IO_ADR_O output and valid data on its IO_DAT_O output. It then asserts its IO_WE_O signal, to specify a write cycle.

• The VGA Controller receives the 12-bit address on its io_ADR_I input and, identifying the addressed register using bits 11..2, prepares to receive data into that register.

• The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The VGA Controller, which monitors its io_STB_I and io_CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by latching the data appearing at its io_DAT_I input into the target register and asserting its io_ACK_O signal – to indicate to the host that the data has been received.

• The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by negating the IO_STB_O and IO_CYC_O signals. At the same time, the VGA Controller negates the io_ACK_O signal and the data transfer cycle is naturally terminated.

Writing to the CTRL Register

The procedure for writing to the VGA Controller's Control register (CTRL) is similar to that detailed in the previous section. There are basically two main differences that apply when the VGA Controller receives the 12-bit address on its io_ADR_I line:

• The address for the register is stored in the 10-bit non-accessible Wishbone Address Register (WAREG), which is loaded as follows:
   
  WAREG <= "0000" & io_ADR_I(7 downto 2)
   
  The value loaded into this register is then interrogated to determine if the internal register being addressed is indeed the CTRL register.

• An internal flag signal is interrogated, to ascertain whether or not the Controller's Wishbone Master interface is currently in use – i.e. Video Memory is currently being accessed. If the Wishbone Master interface is NOT in use, then data from the host processor is latched into the Control register.

Remember that some of the internal registers are not 32-bit. The actual value stored in a register depends on the specific internal register being addressed/written. Table 1 summarizes how the 32-bit data word from the host processor is used by each of the internal registers.

Reading from an Internal Register

Data is read from one of the VGA Controller's internal registers in accordance with the standard Wishbone data transfer handshaking protocol.
 

 
The 10-bit Wishbone Address Register is again used to store the address of the register to be read ("0000" & io_ADR_I(7..2)). The actual data to be sent to the host processor is stored in an additional non-accessible internal register – the 32-bit Wishbone Data Output register (WDOUT).

The read operation occurs on the rising edge of the CLK_I input and can be summarized as follows:

• The host presents the required 24-bit address based on the register to be read on its IO_ADR_O output. It then negates its IO_WE_O signal, to specify a read cycle.

• The VGA Controller receives the 12-bit address on its io_ADR_I input and loads the WAREG register accordingly.

• Having identified the addressed register, the Controller uses that register's contents to load the WDOUT register.

• The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The VGA Controller, which monitors its io_STB_I and io_CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by presenting the valid data stored in the WDOUT register on its io_DAT_O output and asserting its io_ACK_O signal – to indicate to the host that valid data is present.

• The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by latching the data appearing at its IO_DAT_I input and negating the IO_STB_O and IO_CYC_O signals. At the same time, the VGA Controller negates the io_ACK_O signal and the data transfer cycle is naturally terminated.

The actual value stored in the WDOUT register and subsequently sent to the host processor depends on the specific internal register being addressed/read. Table 2 summarizes the 'make-up' of the 32-bit data word that is read back from each register.

Writing to the Active Color Look-up Table (VGA32 only)

Data is written from the host processor to a location in the VGA32 Controller's active color look-up table, in accordance with the standard Wishbone data transfer handshaking protocol.
 

 
When writing to the active color look-up table, bits 10..2 of the io_ADR_I line are used to address the required entry in the table. The two look-up tables are actually part of the same contiguous address space. This 9-bit address provides access to each of the 512 32-bit entries in this address space.

The actual 256 addresses available at any one time depend on the state of the ltb bit in the Control register (CTRL.4). When '0', the lower 256 addresses are addressable (CLUT0), when '1', the upper 256 addresses are addressable (CLUT 1).

The actual 24-bit address sent out from the processor on its IO_ADR_O line is constructed as follows:

VGA32 Base Address + ("1" & CLUT Address & "00")

For example, if the base address entered for the device is 100000h (mapping it to address FF10_0000h in the processor's address space), and you want to write to address 17Fh in CLUT0 (let's assume this is currently the active look-up table), the value entered on the processor's IO_ADR_O line would be:

100000h + DFCh = 100DFCh

The write operation can be summarized as follows:

• The host presents the required 24-bit address, based on the address in the look-up table to be written, on its IO_ADR_O output and valid data on its IO_DAT_O output. It then asserts its IO_WE_O signal, to specify a write cycle.

• The VGA32 Controller receives the 12-bit address on its io_ADR_I input and, identifying the addressed location in the active look-up table using bits 10..2, prepares to receive data into that location.

• The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The VGA32 Controller, which monitors its io_STB_I and io_CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by latching the lower 24 bits of data appearing at its io_DAT_I input into the target location and asserting its io_ACK_O signal – to indicate to the host that the data has been received.

• The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by negating the IO_STB_O and IO_CYC_O signals. At the same time, the VGA32 Controller negates the io_ACK_O signal and the data transfer cycle is naturally terminated.

Reading from the Active Color Look-up Table (VGA32 only)

Data is read from a location in the VGA32 Controller's active color look-up table in accordance with the standard Wishbone data transfer handshaking protocol.
 

 
The read operation occurs on the rising edge of the CLK_I input and can be summarized as follows:

• The host presents the required 24-bit address, based on the address in the look-up table to be read, on its IO_ADR_O output. It then negates its IO_WE_O signal, to specify a read cycle.

• The VGA32 Controller receives the 12-bit address on its io_ADR_I input and, identifying the addressed location in the active look-up table using bits 10..2, prepares to transmit data from that location.

• The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The VGA32 Controller, which monitors its io_STB_I and io_CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by presenting a valid data word ("00000000" & CLUT Data at addressed location) on its io_DAT_O output and asserting its io_ACK_O signal – to indicate to the host that valid data is present.

• The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by latching the data appearing at its IO_DAT_I input and negating the IO_STB_O and IO_CYC_O signals. At the same time, the VGA32 Controller negates the io_ACK_O signal and the data transfer cycle is naturally terminated.