FPGA SI Tutorial - Setting Up

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Modified by Admin on Sep 13, 2017

Before we do any analysis we need to make sure that the components connected to the signals of interest all have the correct models set up. These components are listed below.

U1 FPGA – Xilinx XC3S1000-4FG456C

U5 PROCESSOR – Sharp LH79520

U7, U9 SRAM – Micron MT48LC16M16A2FG-75

U8 FLASH memory – AMD AM29LV640DU90RWHI

U1 is the FPGA. Suitable pin models for all FPGAs supported by Altium Designer are included with the software. The actual pin model that is automatically chosen depends on the final program state of the device, and the settings for pin IO standard, slew rate and drive strength. Part of this example is to determine the optimum settings for these.

Importing IBIS Models

You will need to import the IBIS models for the other ICs listed above in order to have the pin models added to the SI pin model libraries in your installation of Altium Designer. The required IBIS models have been downloaded from the vendor websites and can be found in the \ibis models folder in the example project directory. The IBIS model is imported by editing the schematic component.

Locate U5 on the schematics, and:

Double click to open the Component Properties dialog.
Edit the existing Signal Integrity model, the Signal Integrity Model dialog will open.
Click the Import IBIS button.
Locate and select the IBIS model file for the device.
Select the correct component if a choice is given in the upper region of the IBIS Converter dialog.
Click OK to exit the dialogs. You will be informed that the model data has been written to the libraries, and that the model has been assigned. A report file will open, listing which pin model has been assigned to each device pin.

Now repeat this process for U7, U8 and U9. For the SRAM, there are 3 possible IBIS model files. For this example, we will use y16a.ibs.

Note that we are assuming that the IBIS models from the manufacturer accurately model the pin characteristics. As with any simulation, the models used are extremely important to accuracy. A simulation is only as accurate as the models used!

Another essential requirement for successful SI simulation is to set up supply nets design rules for each of the supply nets (Design » Rules), so that the Signal Integrity Analyzer will handle them correctly. It is particularly important to set up supply net rules for the plane layers. These design rules have already been configured in the example board.

The layer stack for the PCB must also be defined correctly. The Signal Integrity Analyzer requires continuous power planes. Split planes are not supported, so the net that is assigned to the plane is used. If they are not present, they are assumed, so it is far better to add them and set them up appropriately. The thickness for all layers, cores and prepreg must also be set correctly for the board. These properties, as well as dielectric values, can be defined in the Layer Stack Manager dialog (Design » Layer Stack Manager). All such settings have been defined already for the example board.

Initial IO Standard, Slew and Drive Settings

The electrical properties for pins of the physical FPGA device are defined in the FPGA Signal Manager dialog (Figure 1). Access this dialog from the schematic or PCB document using the Tools » FPGA Signal Manager menu command.

Figure 1. Controlling FPGA pin electrical characteristics using the FPGA Signal Manager.

For each pin, the dialog can be used to set the IO Standard, the Slew Rate and the Drive Strength. The available slew rates and drive strengths will depend on the current IO Standard that the pin is set to.

From Figure 1, you can see that the default IO Standard for the data pins has been set to LVCMOS 3.3V. This is the voltage level expected for the signals by the processor and memories in the design.

The Slew Rate for each data pin has been set to SLOW and the Drive Strength to 4mA.

The defined signal information is stored in the corresponding constraint file (IOStandardTest_1.Constraint) for the FPGA project (IOStandardsTests.PrjFpg), with the following parameters added to the corresponding constraint record for the D[31..0] port:

FPGA_DRIVE

FPGA_IOSTANDARD

FPGA_SLEW.

Figure 2. Electrical characteristics added to the relevant constraint file.