Altium Designer 6.3 Release Notes

Frozen Content

Modified by Admin on Nov 6, 2013

Build 6.3.6641

PCB

Major fixes in the Align / Arrange commands
The behavior of Place Rectangular Room command has been improved. Now the mouse cursor snaps to the closest vertex of the room.
Now any of these commands work even after undoing the Align command & applying the same or a different Align command.
Now you can specify a negative clearance. If a clearance rule is not enabled then it will not be used.
Now components will align, as expected, at the bottom side of the bounding rectangle.
Now components will align, as expected, on the left / right side of the bounding rectangle.
When using the Decrease Horizontal tool, the clearance is increased to an appropriate value based on the value set in the rules.
Now it will align the components, as expected, on the left side of the bounding rectangle of the left most component.
Placing Rectangular Rooms will now work as expected. The room will be visible during placement & after placement.
The Place Polygonal Room command has been improved. Now you can see the room segments & the room shape during placement.
The ‘PCB Make Library’ command will now copy across the component height and description fields and the text label TT font fields.
Moving Rooms command has been improved. Now there will be no ghost image of the initial placement of the room when the room is at the cursor. Nor will it be visible at the end of the placement/move command when the position of the room is made static.
The Component Clearance Check has been improved and now works correctly when used in ‘Use Component Bodies’ mode against bottom layer components with no component body defined.
Rotated octagonal pads are now exported correctly to Gerber.
Intermittent access violation associated with the heads up display when closing documents have been resolved
SMD pads containing hole definitions are now reported as warnings in Batch Design Rule Checking. The report contains a link which can be used to automatically convert these pads to equivalent multi-layer pads which can be checked more thoroughly by the system
Via connection style to polygons is now controlled by the polygon connect style rule.
The drawing speed of solid polygons that extend off the screen in GDI mode has been improved
The speed of solid polygon pouring has been improved. This is particularly true when pouring one solid polygon over or around another.
The PCB Print output job has been improved. It is now possible to define a specific board area to print.
The PCB pick popup menu is now more responsive and displays with minimal delay.
Smart Router now allows forced via placement using ‘2’ key. Via is placed while continuing to route on the same layer.
Smart Router now allows dropping vias to planes using ‘/’ key. Via is displayed/placed if net currently being routed can be connected to one of the split planes beneath the via location.
The Pad dialog has been improved. Now the user will not be allowed to edit the hole information for SMD pads.
The mouse cursor X/Y Delta Location will show in Heads Up display even if the X/Y Cursor Location is not enabled.
Now when using the identifier ‘All’ - all the objects in board will be selected.
The handling of multi-layer pads without a valid hole has been improved. Now the user will be warned about their presence when the Batch DRC is run.
The handling of drill SMD pads has been improved. Now any existing drill SMD pads will be automatically converted to multi-layer pads when the user double clicks on such a pad or when changing pad properties in Inspector or List panels.
The Room Placement command has been improved. The rooms will no longer disappear when the current layer is not top / bottom signal.
Increase / Decrease Horizontal / Vertical Spacing commands have been improved. Now the space between the selected objects will be increased / decreased as expected.
Now the component pads will be exported with the correct pad-style instead of the ‘(Default)’ one.
Arcs are now rendered correctly in the PCB 3D viewer.
Solid polygons are now shown in and exported from the PCB 3D viewer.
Significant enhancements to ‘Avoid Obstacle’ mode in the Smart Router.
Adding a PCB Snippet now displays a thumbnail.
Intermittent cursor offset on paste operations has been resolved.
The Clear Filter command from the PCB list panel popup menu now works correctly.
Background loaded PCB documents used in embedded board arrays no longer causes a crash when shutting down the application.
The tab order in the Place Component dialog has been corrected.
The layer attribute of rooms is now available for editing in the object inspector.
In certain situations the board outline could be modified by saving and reloading the document. This issue has been resolved.
Exporting reports with many columns from the PCB list view could sometimes cause corruption in the report. This has been resolved.
A warning has been added when a save is attempted on a PCB or PCB library document with a command active.
The Configure Swapping Information in the Components dialog now shows both placed and total available parts in the Parts column when run on a PCB project.
A bug has been fixed in the Configure Swapping Information in Components dialog. After editing swap information for a component the Part Swap Data column now shows the correct information.
In the PCB pick menu the Enter and Space keys now select the highlighted item.

Embedded

Switching processors in an FPGA project to/from ARM automatically remaps memory and peripherals.
An improvement has been made to correct VHDL syntax error in the discrete Arm wrapper.
Improvements have been made to correctly handle ARM ‘load multiple’ instruction correctly in the wrapper.
Improved speed for switching between Embedded projects
Fixed hang up in huge .c/.h files when trying to show code hints
Improvements have been made to ARM debugger to correctly step over multiplication operations.
Drastically improved the EDIF compilation process. Bus signals will now be properly recognized and compiled in Altium Designer.
Fixed problem in Microblaze when using the value returned by the clock () function, as a full 64-bit integer.

FPGA

Enhancements have been made in FPGA library support. An FPGA Integrated Library for Actel ProASIC3E has been added.
Added a new option for the CPLD flow for Xilinx in the FIT stage ‘Prevent Optimization of Unused Inputs’. This option is off by default.
Examine this option if the user does not wish to resolve the ‘unused input/output’ pin errors from the Xilinx flow.
Issue where Lattice SLEW rate was not being passed to the Lattice vendor tools has been fixed.
The crash experienced after changing CPU type in standalone Schematic documents or in FPGA projects without Embedded sub-projects has been fixed.
Synthesis now checks whether a project has a space in its path and fails accordingly.
Some settings were changed to improve Max7000 optimization. Previously designs were being optimized using speed; now the design should be optimized based on the user setting in the Flow options.
You can now select Actel® and Lattice® bit files from the ‘Choose File and Download’ dialog.
Removed the warning message that reported multiple entities/modules in the same VHDL/VERILOG® file for FPGA projects. This message was no longer needed as this case is now supported.
The crash experienced when opening a saved VHDL Simulation (.SO) file has been fixed. Its now possible to save the .SO file for VHDL simulation and reopen the project
A new wishbone multimaster component (WB_MULTIMASTER) has been added. This component is an extension to the existing WB_DUALMASTER component, supporting up to 8 masters. This component grants bus access immediately when possible and it is optimized for better timing. It supports two modes, priority mode and round robin mode. It also has a special mode for a particular master to have 0 delays. Additionally, it introduces the ability to name the pins of each master. The interrupt pins are included as part of the bus.
An improvement has been made to correct a crash with ‘Create Sheet Symbol from Sheet or HDL’ in the case where a generic or constant was not properly defined.
Two options for the CoolRunner™ II device flow for the ‘Optimize and Fit’ stage have been added. These options are:
‘Enable Default I/O Standard’
‘Default I/O Standard’
‘Sheet Entry not linked to Port’ issues no longer occur when a VHDL file electrically has nothing in it.
Added FPGA_GLOBAL support for Actel®Proasic3. The Altium Synthesizer should now infer CLKINT buffers for Proasic3.
Support for Altera® Quartus 6.0 has been added
Support for Actel® Designer and Actel® Libero 7.1 has been added
When using an EDIF model from Synplicity that outputs the ports of primitives in a different way than the Altium synthesizer. The Altium synthesizer now outputs primitives in the same way as Synplicity does

System-level

2004 SP4 DBLink files are now fully compatible with Altium Designer 6.3
Fixed a bug when exporting a BOM to Excel®. Components with a Type of ‘Standard (No BOM)’ are no longer included in the report.
The BOM report generator for output job documents has been improved. It will now remember the changes made to the exported file format setting.
Out of memory errors no longer occur when dealing with large SchLibs over a period of time.
When typing into the Database Field of a DBLib or DBLink, the case you type in is no longer reflected in the Part Parameter field if it is matching a field name with a defined case.
The SmartPDF command has been improved. Designators for multi-part components now respect the ‘Alpha Number Suffix’ preference setting.
The SmartPDF command has been improved. Dotted and dashed lines with various thicknesses are now correctly exported to PDF.
DBLibs stability has been improved. Database tables can now have any number of columns in DBLibs. Placement of parts is no longer affected by this parameter
The commands ‘Create Sheet From Sheet Symbol’ and ‘Create Sheet Symbol From Sheet’ have been changed. The confirmation dialog ‘Reverse Input/Output Direction’ has been removed
Enhancements have been made to allow the concept of Connectors in constraint files to allow increased configurability of plug-in boards.
A bug where the projects panel would always expand to show the current document when opening or creating a project has been fixed. The expansion of already open projects will not be affected.
Users can now unassociate ‘.dot’ files in system preferences.
The Heads Up Display now correctly refers to ‘Insight Lens’ rather than ‘Magnifier’
In the Parameter Manager Dialog the horizontal scroll bar no longer disappears after executing the copy command
The performance of the Parameter Manager has been dramatically improved when working with large numbers of items and parameters.
The parameter manager now keeps its scroll position after executing a copy.
DBLink has been improved to preserve DB fields/Parts Parameters links when not connected to a Database.
Documents can be removed from projects by dragging them out to an empty space in projects panel.
Limited support is added for Acrobat Reader 5.x.
Fixed bug with scripts when using published Boolean properties. Values assigned to these properties are now applied correctly.
The add PCB component ECO has been improved: now the desired footprint path is taken into account when adding a footprint to the board through ECO.

Schematic Enhancements

The schematic library inspector and list panels have been improved. Hidden parameters will now be shown in those panels for editing.
Previously when adding a model to a component and cancelling out a default model would be added, this has been fixed and no longer occurs.
The placement of part in schematic has been improved: when using the Place Part dialog, the display attributes (font, color, orientation) of the default designator and comment are now properly used.
It is now easier to control the color of power ports placed with the 'Place power port' button. The color is no longer hard-coded in the button and the default power port color is now taken into account.
Items are no longer added to the clipboard panel when Schematic objects are moved by group selection, duplicated, rubber stamped or copied and pasted using shift drag.
Pin/part swap configuration can now be run on schematic libraries. The following changes when running the Configure Pin Swapping command on libraries were made to support this:
When the library is in a PCB project, the dialog now shows the components from the library instead of the components from the project
When the library is in an integrated library package the error 'Failed to compile' is no longer given
The Pin Group and Part Group columns are now editable in the Configure Pin Swapping for Component dialog
The Part No. column is now correct in the Configure Pin Swapping dialog
The Parts column is now correct in the Configure Swapping Information in the Components dialog

CAM Editor

The ODB++ loading has been improved. Allow for single sided boards to load the netlist correctly even if the pads are present only on one side of the board.
CAMtastic®’s Gerber loader has been improved. Now the loader can correctly handle 0 length tracks exported as 0 radius circles when present in the Gerber files in any specific order.
Export commands will not fail anymore because the system can create the user's directory even if more then one sub-directory is specified.
The speed of Export to PCB from the CAM Editor has been improved

Documentation

A new terminology cross reference has been added (GU0121), mapping P-CAD concepts and terms to Altium Designer concepts and terms.
A new application note has been added - AP0145 Working with Version-Controlled Database Libraries. This document provides detailed information on placing components from a database using Altium Designer's SVN Database Library feature.
The tutorial TU0111 Building an Integrated Library has been updated to include a section on creating an integrated library from a database library.
The application note AP0134 Linking Existing Components to Your Company Database has been updated. Information regarding update of parameters from a database has been moved to the new document - AP0144 Keeping Components Up-To-Date.
A new application note has been added - AP0143 Database Library Migration Tools. This document provides detailed information on the migration tools associated with Altium Designer's database library features (DBLib and SVNDBLib).
A new application note has been added - AP0144 Keeping Components Up-To-Date. This document provides detailed information on updating placed components with changes made to those components in source libraries or a linked external database.
The document GU0103 License Service Setup Guide has been updated to include information on the license usage logging feature.
The application note AP0133 Using Components Directly from Your Company Database has been updated. Information on the Integrated Library to Database Library Translation Wizard, and OrCAD® CIS support, has been moved to the new document - AP0143 Database Library Migration Tools.
Information regarding update of parameters from a database has been moved to the new document - AP0144 Keeping Components Up-To-Date.
The article AR0104 Component, Model and Library Concepts, has been updated to include information on version-controlled database libraries (SVNDBLib).
The application note AP0136 Support for PSpice Models in Altium Designer, has been updated with information relating to the support and use of in-line comments.

Translators

The P-CAD importer has been improved. Test points are now imported.
The P-CAD importer has been updated. The printed board region in P-CAD print jobs and the display region in P-CAD design views are now imported.
The P-CAD importer has been updated. P-CAD layer sets are now imported.
The P-CAD schematic importer has been improved. Ports are now imported with the right length.
The P-CAD importer has been improved.
A warning will now be given if the library components do not have unique first 31 characters
P-CAD board outline and cutout objects can now be imported.
Logged messages are now sent to the message panel.
Libraries can now be imported as database libraries.
The OrCAD® PCB importer has been improved.
Mapping an OrCAD® routing layer to an Altium Designer mechanical layer no longer causes a crash.
The importer no longer crashes if there are unused OrCAD® layers.
Free OrCAD® obstacles are now imported
The OrCAD® PCB polygon importer has been significantly improved.
Extra tracks and arcs are no longer added to the polygon outlines.
Duplicate split plane border tracks and arcs are no longer created.
Hatched polygons are now imported with the correct orientation and pitch size.
The OrCAD® importer now imports OrCAD® DSN hierarchy properties.
The OrCAD® DSN importer has been significantly improved.
An option has now been provided to control whether the importer will transform OrCAD® rectangles to use the default Altium Designer color scheme (red border, yellow background).
The importer now ignores garbage library components.
Customized ports are now imported with the correct width and location.
The problem with some invisible properties being imported as visible has now been fixed.
Extraneous parameters ‘Right’ and ‘Bottom’ are now removed.
Images in OrCAD® DSN files are now imported.
Part properties with the name ‘Description’ will now also have their values copied to the component description fields.
The importer now correctly deals with properties where the instance values are different from the values in the design cache.
The ‘PCB Footprint’ field in OrCAD® components is now imported.
Title blocks and their properties are now imported with the correct location.
The imported sheet sizes now correspond more closely to the OrCAD® ones.
The OrCAD® DSN exporter has been improved.
If parameters with the name ‘Value’ exist, they will now be used instead of the comment parameter when exporting schematic components.
The visibility of pin names and numbers are now exported correctly. Also, they are now set to display as rotated on the OrCAD® side.
Schematic parameter positions are no longer shifted after they have been exported.
Power port net names are now exported correctly.
The bounding rectangles of rotated labels and Text-Frames are now exported correctly.
OrCAD® project import: PSpiceTemplate properties on imported OrCAD® parts are now translated to Simulation Models on the schematic components.
The OrCAD® importer has been improved. The names and the Z-order of copper pour obstacles are now imported.
The OrCAD® MAX importer has been improved.
Designators are now imported with the text ‘.Designator’ instead of the actual designator string.
Designators are now attached correctly to their respective components.
Other texts such as package names are also imported.
The width of the default clearance rule is now imported correctly
The OrCAD® importer has been improved: OrCAD® library component references are now imported as default designators.
The IDF export has been improved so that component part names in the IDF library files now match the part names in the IDF board file.