Beta Updates

Altium Designer 6.0.2.5494 Beta
List of Updates

PCB

• The .Legend String now expands correctly in PCB Prints.
• PLOT_FILE_NAME & .PRINTOUT_NAME Strings now expands correctly in in Gerber & ODB++ outputs when TrueType fonts are used.

Altium Designer 6.0.2.5479 Beta
List of Updates

PCB

• Importing changes using show differences has been improved. A crash no longer occurs when comparing a netlist file to a PCB file and producing ECO’s from the differences.
• The reliability of Solid Polygon pours has been improved. It was possible (although rare) for diagonally adjacent objects to cause the polygon pour to unexpectedly cause shorts or clearance violations. This issue has now been resolved.

Manufacturing

• Gerber and ODB++ Manufacturing outputs have been improved. Component Designator and Comments using True Type fonts that are hidden in the design are no longer incorrectly exported to these formats.
  Schematic
• Right-mouse-clicking into the void on a schematic just after Altium Designer 6 is started no longer incorrectly displays Part Actions -> Configure Pin Swapping menu-item.
• The schematic part preview in the library panel now always scales correctly and no longer clips the component under certain circumstances.
• Wires no longer move unexpectedly in schematic when placing a new wire that ends on the same X or Y coordinates as an existing, selected wire.

Altium Designer 6.0.2.5430 Beta
List of Updates

Simulation

• XSPICE component SXFER bug has been resolved. Coefficient values are now de-normalised correctly producing accurate results in a Transient Analysis.

FPGA

• Resolved an issue where LVDS was not being passed properly to Spartan-IIE Devices.
• Resolved issue where the FPGA_IOSTANDARD attribute was not properly being passed to the vendor tools for some cases.

Altium Designer 6.0.2.5413 Beta
List of Updates

PCB

• The PCB Board Layers and Colors dialog has been improved. It’s now possible to select multiple layers and change their visibility status by toggling or turning all on or off.
• The Board Insight preferences have been improved. Entering Lens configuration data now persists correctly both using the Spin Edit and Slider controls.
• The fabrication output reports have been improved. The Extension Report and Status Reports now correctly display layer names as defined by the user in the PCB design rather than the system default names.
• NC Drill output has been improved. Vias with reversed Start and Stop layers are now exported correctly.
• The Make PCB Library command has been improved. Region objects belonging to components are now correctly populated through to the generated library.
• Display of the PCB special string .PCB_FILE_NAME has been enhanced. The converted filename is no longer truncated when displayed on the PCB.
• Verify shorting copper of Net Ties during PCB Design Rule Check now functions correctly.

Schematic

• Fixed drawing of negation bar over net label
• Fixed bug when placing note polygons.
• The auto sheet entry feature has been improved: the name of the automatically placed sheet entry now respects the case of other connected objects names.
• The editing of PCB rule directives in schematic has been improved; such a directive now retains correctly the PCB units that were used previously.
• When using the Schematic Rubber Stamp and moving the mouse while holding down the mouse button when pasting, the cursor origin no longer moves.
• 'Formatting' toolbar has 3 new buttons:
• Line or border width
• Line style
• Line ends shapes and sizes
• When placing parts from the Place Part dialog, if multiple libraries share the same LibRef, selecting one component to place no longer places a different component from another library with the same lib ref.
• Object Property dialogs, Inspector and List panels now show images in dropdown lists to help select appropriate line or border width, line style or line end shape and size.

Scripting

• It’s now possible from scripts to change project variants, using interfaces IProjectVariant, IComponentVariation and IParameterVariation

FPGA

• An enhancement has been made to the Altium Synthesizer to take advantage of hardware multipliers in FPGA. Available FPGA hardware multipliers will be used when a multiplication operation is found in the design. This is available for both signed and unsigned multiplication.
• An option to remove redundant logic using the Altera Synthesizer has been enabled. This should decrease the area for designs.
• Some settings were changed to improve Max7000 optimization. Previously designs were being optimized using speed; now the design should be optimized based on the user setting in the Flow Options.
• Improvements have been made to the PPC405A wrapper to allow program code to execute in the external memory correctly.
• When using an EDIF model from Synplicity that outputs the ports of primitives in a different way than the Altium synthesizer the Altium synthesizer now outputs primitives in the same way as Synplicity does.

Embedded

• Examples now support the new demo boards with Xilinx XC3S1000 FPGA.

Platform

• The Messages panel and ECO dialog now show popup tool-tips when the mouse is over a cell where the text doesn't fit on screen.
• File Type associations can be now fully restored from Preferences - System - File Types dialog.
• When compiling a single Schematic document from an FPGA project the check for unique IDs is no longer performed.
• Validating an ECO using "Move Pins To Different Nets" no longer causes a crash.
• The differential pair pin error reporting has been improved. It no longer incorrectly reports 'Net not connected to differential pair pin' under specific circumstances.
• Improvements have been made to the Storage Manager to correctly display project files when Altium Designer is opened.
• Fixed a crash that occurred while loading text documents with no extension in the file name.

Altium Designer 6.0.2.5339 Beta
List of Updates

PCB

• PCB Print options dialog now allows multiple layers to be selected for batch removal and move up and down.
• Some memory optimizations have been made to the "Update from PCB Libraries" command to prevent out of memory exceptions.
• The “Update from PCB Libraries” command now takes into account component description and height fields.
• The "Update from PCB Libraries" command has been improved. All layers can now be selected for comparison and extra duplicate objects no longer cause a problem for the comparison process.
• The P-CAD PCB exporter has been improved. Exporting component bodies no longer cause a crash.
• Problems with updating free primitive's nets from component pads have been fixed.
• The efficiency of Add/Remove pin ECO's has been improved and the extra options for updating primitive nets have been removed.
• The "Explode Component to Free Primitives" command has been improved to allow all selected components to be exploded.
• The PCB DRC has been improved. Allow Short Circuit constraints no longer cause incorrect violation counts.
• The Component Rule Check for PCB Libraries now correctly links to the generated file in the project.
• Some memory leaks in PCB utility servers have been removed.
• Generating a DRC report requiring Net Tie verification no longer crashes.
• Changing a track from a net to no net now correctly clears the net name text from the track.
• Component Drawing has been improved. Empty comments no longer appear as a small square on selected components.
• Large numbers of selected primitives in the PCB panel no longer cause extended delays in clear mask operations.
• Polygons are now shown correctly in the Board Insight Panel and Popup windows.
• Failed calls to Alpha Blending routines during PCB drawing are now detected and the system is automatically reconfigured to disable the use Alpha Blending.
• An Access Violation when clicking on the All Components Class in the Design Classes dialog on certain designs has been fixed.

Schematic

• Fixed occasional access violation when editing models in schematic libraries or documents.
• Find Similar Objects dialog now works for all coordinate units.
• New hotkeys for navigating the different channels in multi-channel schematics are available. The hotkeys are + and -, and also CTRL+SHIFT+mouse wheel.
• The schematic shortcut keys E then R for Redo now works properly.
• Hidden pins are no longer ignored when saving schematic libraries to Protel V4 format.
• When ports, sheet entries or sheet symbols are masked by a compilation mask, they are no longer taken into account when doing port / sheet entry synchronization.
• AutoFocus zooms onto text objects more predictably .
• ‘Synchronize Ports to Sheet Entries’ dialog now works with multi-selection. The first selected sheet entry is associated with the first selected port, the second selected sheet entry is associated with the second selected port, and so on. If the selection numbers are not equal, the 'extra' selections (on either side) are ignored. The tooltips for the synchronize buttons now show names of all ports/entries to be matched. It's also possible to unmatch more than one link at a time.
• The schematic list panel no longer crashes when past text into the Pin Electric type column.
• Performance problems with the List and Inspector panels when pasting large numbers of items into Schematic documents have been resolved.
• Sheet Entries position field is now displayed in document units in the list and inspector.
• Selecting a different part in the component properties when no library path is specified in a database library no longer causes an AV.
• The schematic ComponentLink reference has been fixed. Opening a PDF from the web now works correctly.
• The P-CAD schematic importer has been improved. The rotation of flipped attributes are now imported correctly.
• The schematic inspector and list panels have been improved. Changes to the "Library Reference" field will now correctly update the component.

Mixed-Signal Simulation

• Fixed an issue causing subcircuits referenced from within another subcircuit to be omitted from the generated XSpice netlist file. This occurred generally where there was more than one subcircuit referenced.
• The polynomial controlled source conversion was not being done when the spice line began with a space. This was causing an access violation during simulation. This has been resolved.
• Fixed problem in Pole-Zero analysis that was causing the following error to occur 'doAnalyses: Unknown error code detected in routine "VCVSask"'.
• Fixed an issue in XSpice where leading plus signs, and plus signs in exponents were not being parsed correctly.

Signal Integrity

• Fixed crash that occurred in Signal Integrity after modifying the model assignments.

CAM Editor

• It’s now possible to save the DRC settings in CAMtastic® using the Save command in the "PCB Design Check / Fix" dialog.

Processor Support

• Problems with running the new TSK165 processor on Altera FPGAs have been resolved.
• Problems debugging with MicroBlaze processors have been resolved.

FPGA / PCB Integration

• Auto-generated PCB project now contains FPGA Power & Configuration ports as specified in the wizard’s options.

Platform

• Exception reporting is now available (for beta testers).
• Projects panel no longer crashes when loading P-CAD netlists that can’t be accessed by the user due to file permissions.
• XML files now have correct icon in the documents bars.
• Fixed appearance of Text editor - Color page in Preferences dialog on Japanese locale.
• Adding scripts to toolbars by using drag/ drop from the function name now works the same as using the Customize dialog.
• Improvements have been made to Storage Manager to prevent unnecessary refreshes that show a progress bar.
• Storage Manager now focuses correctly on the target document when switching between documents.
• Storage Manager now focuses on the correct document after closing a history file.
• Fixed problems opening multiple html report documents.