Altium Designer 6.0.2 Release Notes

Altium Designer 6.0.2.5495

PCB

• The PCB DRC has been improved. Allow Short Circuit constraints no longer cause incorrect violation counts.
• Fixed problem with opening multiple html report documents
• The robustness of Component Classes in the PCB editor has been improved. Previously boards with large numbers of components could cause some instability which typically presented as an access violation in the Design Classes dialog.
• Display of the PCB special string .PCB_FILE_NAME has been enhanced. The converted filename is no longer truncated when displayed on the PCB.
• The Make PCB Library command has been improved. Region objects belonging to components are now correctly populated through to the generated library.
• The Component Rule Check for PCB Libraries now correctly links to the generated file in the project.
• Some memory leaks in PCB utility servers have been removed.
• The PCB Board Layers and Colors dialog has been improved. It is now possible to select multiple layers and change their visibility status by toggling, turning all off or turning all on.
• Generating a DRC report requiring Net Tie verification no longer crashes.
• The efficiency of Add/Remove pin ECO's has been improved.
• The "Explode Component to Free Primitives" command has been improved to allow all selected components to be exploded.
• Changing a track from a net to no net now correctly clears the net name text from the track.
• Component Drawing has been improved. Empty comments no longer appear as a small square on selected components.
• Large numbers of selected primitives in the PCB panel no longer cause extended delays in clear mask operations.
• Polygons are now shown correctly in the Board Insight Panel and Popups
• Signal Integrity model assignment has been improved. Modifying model assignments no longer causes an access violation.
• Failed calls to Alpha Blending routines during PCB drawing are now detected and the system is automatically reconfigured to disable the use of Alpha Blending.
• Verify shorting copper of Net Ties during PCB Design Rule Check now functions correctly.
• The Board Insight preferences have been improved. Entering Lens configuration data now persists correctly both using the Spin Edit and Slider controls.
• The reliability of Solid Polygon pours has been improved. It was possible (although rare) for diagonally adjacent objects to cause the polygon pour to unexpectedly cause shorts or clearance violations. This issue has now been resolved.
• Importing changes using show differences has been improved: when comparing a netlist file to a PCB file and producing ECO’s from the differences, a crash no longer occurs
• What’s This Help added to the Change Component Body dialog in the PCB Library Editor.
• What’s This Help added for the True Type font options in the PCB Editor Component dialog.
• The P-CAD PCB exporter has been improved. Exporting component bodies no longer cause a crash.
• Some memory optimizations have been made to the "Update from PCB Libraries" command to prevent out of memory exceptions.
• Fixed crash when loading text documents with no file name extension.
• The "Update from PCB Libraries" command has been improved. All layers can now be selected for comparison and extra duplicate objects no longer cause a problem for the comparison process.
• The PCB Print options dialog has been improved. In the printout properties dialog, multiple layers can now be selected for batch removal, move up, and move down.
• The comparator in the "Update From PCB Libraries" command has been improved to take into account component description and height fields.
• The .Legend String now expands correctly in PCB Prints.
• .PLOT_FILE_NAME & .PRINTOUT_NAME Strings now expands correctly in in Gerber & ODB++ outputs when TrueType fonts are used.

Manufacturing

• It is now possible to save the DRC settings in CAMtastic® using the Save command in the "PCB Design Check / Fix" dialog.
• NC Drill output has been improved. Vias with reversed Start and Stop layers are now exported correctly.
• The fabrication output reports have been improved. The Extension Report and Status Reports now correctly display layer names as defined by the user in the PCB design rather than the system default names.
• Gerber and ODB++ Manufacturing outputs have been improved. Component Designator and Comments using True Type fonts that are hidden in the design are no longer incorrectly exported to these formats.
  Schematic
• "Toolbar 'Formatting' has 3 new buttons to set
• Line or border width
• Line style
• Line ends shapes and sizes"
• Objects property dialogs, Inspector and List panels now show images in dropdown lists to help select appropriate line or border width, Line style or Line end shape and size.
• AutoFocus zooms on text objects more predictably, when 'Restrict To Net Identifiers only' option is checked, or at some zoom levels when this option is off.
• 'Synchronize Ports to Sheet Entries' dialog now works with multi-selection. The first selected sheet entry is associated with the first selected port, the second selected sheet entry is associated with the second selected port, and so on. If the selection
• The schematic inspector and list panels have been improved. Changes to the "Library Reference" field will now correctly update the component.
• The schematic multi-channel navigation has been improved. The keys + and -, and the mouse control CTRL + SHIFT + wheel are now mapped to scroll through the multi-channel tabs displayed at the bottom of the schematic editor.
• The "R" accelerator key for Schematic Smart Paste has been removed as it conflicts with the one for Redo.
• The schematic library saving process has been improved. Hidden pins are no longer ignored when saving to V4 format.
• The P-CAD schematic importer has been improved. The rotation of flipped attributes are now imported correctly.
• The schematic inspector has been improved to show the sheet entry position in document units.
• The schematic ComponentLink Reference has been fixed. Opening a PDF from the web now works correctly.
• Fixed bug in Pole-Zero analysis that was causing an unknown error code to be falsely generated.
• PCB AutoGenerated Sheet now adds FPGA Power & Config Ports properly
• The schematic list panel has been improved. Crashes no longer occur when pasting into the Pin Electric type column. The performance problem with pasting large number of entries has also been resolved.
• Fixed drawing of negation bar over NetLabel
• Fixed bug when placing note polygons.
• What’s This Help added to the Place Sheet Entries Automatically option in the Preferences dialog.
• What’s This Help added to the Group Undo option in the Preferences dialog.
• Selecting a different part in the component properties when no library path is specified on a DBLib no longer causes an AV.
  FPGA
• Some settings were changed to improve Max7000 optimization. Previously designs were being optimized using speed, now the design should be optimized based on the user setting in the Flow Options.
• Enabled an option to remove redundant logic using Altera Synthesizer. This should decrease the area for designs.
• When using an EDIF model from Synplicity that outputs the ports of primitives in a different way than the Altium synthesizer the Altium synthesizer now outputs primitives in the same way as Synplicity does

Platform

• Fixed appearing of Text editor - Color page in Preferences dialog on Japanese locale.
• File Type associations can be now fully restored from Preferences - System - File Types dialog.
• Messages panel and ECO dialog now show popup tool-tips when mouse is over a cell, where text doesn't fit on screen.
• Improvements have been made to Storage Manager to focus on the target document when switching between documents.
• The projects panel has been made more robust so that it won't crash when loading P-CAD netlists that can't be accessed by the user due to file permission problems.
• Improvements have been made to Storage Manager to focus on the correct document after closing a history file.
• Fixed icon of XML document in documents bar
• The ECO generator has been improved. Validating the ECO modification "Move Pins To Different Nets" no longer causes a crash.
• When compiling a single Schematic document from an FPGA project the check for unique IDs is no longer performed.
• "A new application note has been written - AP0134 Linking Existing Components to Your Company Database.pdf - which replaces the following previous documents:
• TU0119 Linking from a Company Database to Components in Your Design.pdf
• TR0128 DatabaseLink Ed"
• "The DatabaseLink Editor Reference document (both PDF and HTML versions) has been superseded by the following document:
  AP0134 Linking Existing Components to Your Company Database.pdf"
• The application note AP0134 Using Components Directly from Your Company Database.pdf has been updated to include information on the Integrated Library to Database Translation Wizard.

Scripting

• It is now possible from scripts to change project variants, using interfaces IProjectVariant, IComponentVariation and IParameterVariation
• Improvements have been made to Storage Manager to prevent unnecessary refreshes that show a progress bar.

Mixed Signal Simulation

• Fixed an issue causing sub-circuits referenced from within another sub-circuit to be omitted from the generated XSpice netlist file. This occurred generally where there was more than one sub-circuit referenced.
• The polynomial controlled source conversion was not being done when the spice line began with a space. This was causing an access violation error during simulation. The issue has now been fixed
• Fixed an issue in XSpice where leading plus signs, and plus signs in exponents were not being parsed correctly
• XSPICE component SXFER bug has been fixed. Coefficient values are now de-normalised correctly producing accurate results in a Transient Analysis.

Libraries

• Altera Cyclone II.IntLib
• Maxim Interface Line Driver.IntLib
• Xilinx Spartan-II.IntLib
• Xilinx Spartan-IIE.IntLib
• FPGA Peripherals.IntLib