Altium Designer 2004 - Service Pack 1
Altium Designer 2004 SP1 highlights include significant updates to Protel’s autorouting technology, and the addition of Spartan-3 device support to Nexar. The following list presents a complete list of updates and enhancements made for Service Pack 1 for Altium Designer.
Release notes
Release Notes from Build 8.0.4.1272 to Build 8.1.4.1717
Design Capture
2638 Carriage Return characters are no longer displayed as boxes in Schematic Text boxes
2645 Text in the heading of the 'Update From Library' dialog is no longer editable
5333 Redirection feature now working correctly, parameter values are displayed in the Navigator panel and passed to the PCB and BOM
5337 The default electrical grid has been reduced to 4 to stop perpendicular wire segments that are placed between 2 adjacent pins creating a short. This change applies to new/current Protel 2004 schematics and imported Protel DXP and 99SE schematics
5340 Junction and manual junction connection status markers are now displayed properly when a Schematic selection is pasted in Word
5911 Component Parameters added from Simulation or Signal Integrity models are now appearing in the correct location
6255 Look of the Advanced tab in the Database Connection dialog has been reviewed
6256 Look of the Database Link Options dialog has been reviewed
6257 The Key field in a Database Link is no longer disabled once you start editing
7713 The database grid is no longer disabled after selecting the single key lookup radio button
7714 The contents of the Database field drop down list in a DbLink doc no longer disappears after switching
7926 It is now possible to select a set of components in a schlib and paste them in a sch document
8106 Non active sheets no longer have their zoom level changed while cross probing
8374 DBlinks now remember their look-up type when opened
8523 A catastrophic failure is no longer created when editing a schematic document that contains 0 radius or secondary radius ellipses
8600 The Schematic query keyword 'Object_TargetFileName' is now recognised
10822 In a Schlib, Object Inspector now pops up properly when using the Find Similar Dialog with the Run Inspector option
11029 Added a tool 'Number Sheets' in order to easily manage the DocumentNumber, SheetNumber and SheetTotal system parameters. This tool can be invoked with the 'Tools » Number Sheets' command.
11032 A new option, Sheet Number Spaces, has been added to Design » Document Options to allow more room for sheet number
874787 Performance has been enhanced while editing a component in the Schematic Library
Text Editor
6628 Performance has been improved to reduce the delay in displaying information in the Code Explorer when a file is loaded
6631 A new option 'Open changed files in editor' has been added to the Replace in Files dialog
6632 Drop down history list in the Text Editor search now selects the correct option
6633 Code templates can now be selected correctly in the VHDL editor
6634 Smart TAB in the Text Editor has been improved as well as word left, word right
6635 Template list pop up window is now sizable
6636 Text to Find field now appears blank in Find Text dialog when cursor is on white space
7046 Changing the preferences of one text editor is no longer affecting the preferences of other editors
8107 Copying/Pasting of collapsed text works correctly without loosing parts of the function
8116 New features added to the text editor to capitalize word or selection
8117 Code Templates are now working properly
8118 The font used when hovering with your mouse on the collapsed text is now aligning correctly
8119 The cursor no longer moves to the top of a text file after selecting the Save Copy As command
8120 Global Find & Replace is now able to change more than one item on the same line correctly
8296 The Smart Tab feature has been optimised to tab to the previous line correctly
Design Compiler
1260 An Access Violation is no longer caused when Showing Differences on a project with no schematic
6612 Compiling a project no longer changes the active project if it would break the link between the current project and the current document
8344 A catastrophic failure no longer occurs when compiling a Protel 2 net list containing rules
PCB To FPGA Links
8080 FPGA projects and associated schematic documents can now be located in separate directories to the PCB project
8081 FPGA Workspace View no longer causes a crash when a PCB project is linked to an FPGA project with no schematic documents
Online Help
7270 What's this Help now works correctly in Project Simulation Option dialog
7271 What's this Help now works correctly in Project Synthesis Option dialog
8040 Topics for 'Modifying PCB/Schematic objects and updating the Undo system' has been added into the Help system in order to cover the Undo feature in DXP scripting
General
2493 Focus now stays on the OK button in the Windows » Close All dialog after selecting Save None with Alt+N
5501 Memory cores are now better optimised for cases where the depth is not a power of two
6862 The user no longer needs full Administrator rights on their work station to run the software, the parallel port driver is now installed during software installation
6955 Running certain WorkspaceManager Processes no longer causes a Catasrophic failure
8176 New operators added to the query language; && and ||. These act like in C, having lower precedence than comparison operators.
10958 IPCB_Pad.Name no longer causes access violation when set from a script
FPGA
5117 Xilinx Spartan 3 FPGA device support has been added. All Spartan 3 devices are now detected and supported in the FPGA process flow in the Devices View
5501 Memory cores are now better optimised for cases where the depth is not a power of two
5511 The Logic Analyzer Menu and Toolbars are now disabled when the document containing the Logic Analyzer instrument is not open
5515 The Core Generator now provides general information about the core being elaborated in the messages and output panels
5582 Improved checking of file time stamps while compiling to ensure correct generated documents are added to a project
6613 An option called SwapID has been added in the Constraint file editor when adding a constraint file
6787 Trigger Setup information is now stored as parameters of the FPGA project
6789 Save Changes dialog now displays when closing Logic Analyzer via the instrument panel check box
6788 In the logic analyzer, cursor A no longer tracks cursor B when it is dragged
7540 Support for Xilinx ISE 6.2 has been added
7679 Generated Xilinx ISE project files are targeting the correct CoolRunner2 devices
7680 The system for synthesizing signals with IO Standards has been revised and should now work correctly with all supported devices
7681 Moving a configuration file in the structure editor correctly flags a project as modified
8008 Altera Quartus II V4 is now supported
8184 Correct speed grade is now being passed to Xilinx ISE to build FPGA projects
Library Management
5339 Aliases of a component are now displayed correctly in the libraries panel, when the component is part of a schlib
6652 Opening the same IntLib document twice no longer leaves an empty LibPkg in the Projects Panel after a Close All
6570 Rotation and Translation values of 3D models are now saved
6572 Cylinders and spheres are now drawn when a 3D model is first selected in 3D library editor
6642 Changing the background color with a PCB3DLib file open now works correctly
7462 System no longer halts when compiling an integrated library containing 3d models, while 3d library is open
7676 IO standards have been updated for the SSTL18C1/2 to Virtex2 and PCI66 removed from MAX3000A
8084 Spartan3 Nexus drivers have been added to support the Spartan3 devices
8362 Double click on panel trackball in 3d library now repositions component to default
8365 Open dialog no longer appears when double clicking on the text 'Selected 3D model'
8371 Export to IGES option is now disabled when no component is selected
8509 F1 for a component in the FPGA Generic Library now operates correctly
8620 File » Save As now works correctly when saving from the PSC 3D Lib editor
10782 A legend has been added to the PCB3D Lib Panel to show which color is which axis and which end of each axis is positive
License Management
7466 Improved activation error messages when incorrect customer number is used
7660 Evaluation licenses now stop working at midnight on the expiry date
8369 Home link now goes to DXP Home after a failed activation
8377 A message now notifies you when an invalid evaluation licence is used
8430 Node locked licenses now require a MAC address or a hard disk. Previously a MAC address was always required
10785 Adding a second ALF file with the Activation code now reports that you should not do this
LiveDesign View
4439 Live, Ignore FPGA source and Ignore Software options are now disabled in the Nexus Workspace Preferences dialog when building a design
7519 Removing devices from the Devices View while building, no longer causes a List Index out of Bounds error
7582 Device View is now locked when running a process flow
Mixed Signal Simulation
3635 Temperature sweep now uses all sweep values correctly, and negative temperature values are supported
3637 Hints are now shown on the status line when the mouse pointer is placed over a temperature sweep wave
6803 An exception error is no longer created when running a Monte Carlo analysis with a comma as the decimal separator
PCB Design
5950 DRC can now detect unrouted power nets, when routed to a Blind or Buried Vias that do not pass through power planes
6896 Connection lines are now refreshed after importing a board that has been routed by Specctra
7050 The correct values are now being shown in the Board Information report when the Selected Objects Only option is enabled
7120 The Whole Library checkbox in the PCB Library list panel now functions correctly
7475 The Object Inspector panel is now kept up to date correctly with the PCB List view
7485 Routing Layers Design Rule now displays layers used for auto routing in stack order
7687 Manual Pin Swapping now only swaps pads from same group
7815 Changes to Track & via sizes no longer effect design rules
7818 'IsPolygon' is now being detected and flagged as an error in the clearance rules
8173 The accelerator key for the menu item Simple BOM has been changed to the letter O to remove a conflict of options
8393 PCB Special Strings are now interpreted properly when edited and the Convert Special Strings options is enabled
873397 On-line DRC has been updated to support the 'Full Check Component Clearance' rule
873748 PCB rule names are now preserved when synchronizing PCB documents from Schematic
PCB Design - 3D Viewer
7467 A STG Exception error is no longer created when viewing boards in 3D and there is no 3D library available
7468 Minor issues fixed in export and import dialogs for PCB 3D view and library. File type, igs extension, is now included in save as dialog from Tools » Export IGES model in PCB 3D view. In PCB 3D library, a message now appears when an invalid filename has been entered when importing a 3D model
7471 Option added to IGES export to export only components with a size along any axis greater than a specified minimum
7546 The file extention igs is now added to IGES files when they are exported from the 3D viewer
8360 Additional options added to the Tools menu in the PCB 3D Lib editor; Rename, Delete and Set Rotation and Translation
8366 3d view no longer draws twice when first opened
8370 IGES export options controlling which board holes are exported now works correctly
PCB Design - PCB Autorouting
7484 Various improvements to the way Situs uses memory resulting in less memory fragmentation and improved performance
7486 Situs now includes a comprehensive Routing Setup Report section in the setup dialog.
Features include:
- Hyperlink formatted report.
- Ability to save report in HTML format.
- Tests for unroutable pads.
- Error details included in report
- Number of affected primitives displayed in report
- New Edit Layer Directions dialog
7489 Memory leak has been fixed when a design rule has an InNetClass scope and the class does not exist
10920 New orthogonal routing strategy and recorner pass added
10922 Situs Fanout to power plane now uses BGA style dogbones when appropriate
10923 Autorouter improvements made to copper sharing routes such as overlapping tracks and branched routing
874026 Pre-routed and locked vias are now handled correctly providing improved routing performance.
874056 Support for Via to Via clearance rules on the same net has been improved. This has significantly improved the routing performance on boards that use this rule.
874081 Connectivity to split planes has been improved
PCB Design - PCB Manufacturing - Fabrication
5948 An Exception error no longer occurs when generating ODB++ output on certain designs
6908 Variations in the Tool Table *.mts file header are now recognised
7669 CAMtastic® now detects Net Antennas correctly
8142 Now you are able to change exported Gerber extension for selected layers also
8143 Metric to inch conversion issues resolved with the Drawing Modes dialog and Venting Borders when panelizing
8144 CAMtastic® Quick Load correctly imports IPC files containing keywords that usually appear in NC Drill files
10946 The 'View » Views » Negative' command is now available in both CAM and NC editors in CAM documents
Printing
6252 Paper Size is no longer reset to A4 when changing settings in the Advanced Setup Printer properties dialog
6879 Schematic sheets now print in the correct order and are based on the Sheet Number
7058 Performing a Print Preview for the first time no longer resets all the page options to their default
11030 In print preview a printer icon is now displayed on the thumbnail view of pages that are selected to print
Project & Document Management
4403 Columns in the Edit Search Path dialog and in the Search Path of the Options for Project dialog remain unchanged when pressing the Refresh List button
6695 Shared documents in multiple projects are now highlighted correctly when the focus is in the Projects Panel
7626 An Access Violation no longer occurs when selecting Ctrl+F9 in the Fabrication Outputs Outjob file when there is nothing selected
8281 Clarified wording of Library Options tab of project options for Integrated Library
8373 Variant information is no longer lost when brining a design from an earlier version
8423 A new check box has been added to the Comparator Tab of the Project Options dialog to Ignore Rules Defined in the PCB Only during design comparison. This ensures that the ECO no longer attempts to remove default PCB design rules or rules that have been manually added to the PCB document
8431 Having a large number of projects open at the same time no longer creates high CPU usage when the application is idle
10944 The catastrophic failure caused by removing a document from a project via the right click has been resolved
Signal Integrity
7682 Improvements to Manhattan length routing
8076 SI will switch to single pulse stimulus when a PCB exists, if previously run was in Schematic only mode using constant level stimulus
8079 You can now define different stimuli for concatenated nets when running a Signal Integrity
8085 Improved error reporting while importing IBIS files
8086 SI setup helper no longer removes models edited in advanced mode
User Interface Management
6043 Sorting and filtering is now working correctly in the Table Browser of Database Link files
6630 The PCB and SCH list panels no longer allow the cursor to be located past the end of a line
6944 The Messages panel is now using the regional setting to format the time
6961 Processes selected in the Process Browser dialog are now saved in the Process drop down list of the Run Process dialog
7123 The Info buttons in the Run Process, Process Browser and Customize Edit Command dialogs correctly displays information when information exists about the current process
7160 Tool Tip description in the Navigation toolbar changed from 'Go Home page' to Go to Home page'
7297 The predefined filters accessed via the Y shortcut key all function correctly now
7513 Show Waves button correctly shows the LaxDig and LaxAn files when they are open
7917 The system font is no longer set to disabled when starting the software
8398 An exception is no longer caused when closing after saving a desktop layout
8566 Using fractal panels no longer causes an access violation on exit of application
8596 The cursor can no longer be placed after the end of the text in the Query Helper dialog
VHDL
7124 Default Optimization Level option has been set to 2 when using the XST synthesizer
7604 The VHDL Simulation waveform window is now being refreshed correctly
7750 mif files generated during synthesizing are no longer empty
7999 Changes to VHDL Simulation include:
- New waveform option has been removed from the FPGA Preferences dialog. The same waveform is used all the time unless saved manually.
- Moved Show signals at Startup options from FPGA Preferences dialog to the Signals dialog.
- The Add Watch dialog now displays a combo list of all possible watches.
- The wave document is not resized each time a simulation operation occurs, instead it's just refreshed.
- Simulation status dialog has been removed. Progress of compile/simulation is now in the status bar.
- Abort is located in Simulator » Abort compile.
8002 In VHDL Synthesis, the percentage progress bar has been added to the status bar
8009 Options in the VHDL Synthesis Options dialog are now saved correctly
Waveform Viewer
6804 'Exception in Safecall Method' no longer occurs during a simulation when moving the mouse in the SimView Chart page
6946 The 'Depth of Hierarchy to Display' dialog in the SO file has been reformatted to follow the standard style.
6947 The 'Jump To Time' dialog has been reformatted to follow the standard style
6948 The 'Choose Cursor dialog' has been reformatted to follow the standard style
8346 Signal Names in .SO documents are now displayed properly and respond to movement in signal widths