Hardware Acceleration

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Hardware acceleration is the concept of enhancing the speed of a design by imparting software processes into hardware. Many computational algorithms that are straightforward to code and debug in software are inherently parallel in nature. Encryption algorithms, image manipulation and signal processing are just some examples. To remain as software entities, such functions place heavy demands on the processor. FPGAs themselves are parallel in nature, offering the ability to perform multiple operations simultaneously. To move computationally-intensive functions from software into hardware, and ease the burden of the processor, would therefore be considered an evolutional jump for the design.

In Altium Designer, hardware acceleration is facilitated using the C-to-Hardware Compiler (CHC), which takes standard untimed ISO-C source code and produces a synthesizable hardware file (RTL). Upon synthesis, this RTL description is translated into an electronic circuit that implements the function required. A 'soft' processor in the FPGA design accesses these hardware functions through use of an Application-Specific Processor (ASP).

Figure 1. The ASP component interfaces between the code running on the processor and the functions implemented in the FPGA fabric.

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