Designing Custom FPGA Logic using C

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Altium Designer provides the ability to add custom logic to an FPGA design, where that logic is 'captured' in an underlying C source file, and referenced using a C Code Symbol primitive. The latter is a type of sheet symbol that is essentially used to 'export' a single top-level function from the referenced C source file – passing it to the C-to-Hardware Compiler.

Simply write the functionality required in the comfort of Altium's code-aware C Editor and then sit back as the CHC technology converts the code into VHDL or Verilog (depending on your defined netlisting preference). Armed with even a basic software background, there is now no reason why you can't design custom FPGA logic!

All source C (and header) files containing functions to be exported must be added to the FPGA project. This allows the C-to-Hardware Compiler to find the files for subsequent HDL generation.

The ability to incorporate underlying C code into an FPGA design is an extension to the concept of design hierarchy. Similar to the way in which a schematic sub-sheet or HDL file (VHDL/Verilog) is referenced by a Sheet Symbol on the parent design schematic, the C source file is referenced, as mentioned previously, by use of a C Code Symbol.

Hierarchical net and bus connectivity between documents obeys the standard hierarchical project connection behavior, where parameters for the referenced function in the C source file connect to C Code Entries of the same name in the C Code Symbol that represents that document, as shown by example in Figure 4. The C Code Entries allow for connection to other logic in the design.

Figure 1. Adding custom logic through creation of hierarchical FPGA designs.


It is also important to remember that each C Code Symbol is associated with only one top-level exported function in a C source file. However, this exported function may call other functions, which themselves may be distributed across several C source files.


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