Accelerating Processor Systems

Frozen Content

Modified by Admin on Sep 13, 2017

In many processor systems, the embedded processor is charged with handling computationally-intensive algorithms. These algorithms place a burden on the processor, which can have a significant impact on intended performance. The performance of such designs can be greatly enhanced if these algorithms were moved to hardware, as circuits in the FPGA fabric itself, and that's where Altium Designer's CHC technology comes in...

Providing Hardware Acceleration

Hardware acceleration is the concept of enhancing the speed of a design by imparting software processes into hardware. Many computational algorithms that are straightforward to code and debug in software are inherently parallel in nature. Encryption algorithms, image manipulation and signal processing are just some examples. To remain as software entities, such functions place heavy demands on the processor.

FPGA devices are also parallel by nature, offering the ability to perform multiple operations simultaneously. To move computationally-intensive functions out of the software domain and into the hardware realm – through the use of C-to-Hardware compilation technology – not only eases the burden on the processor, but can also give your design a substantial boost in the speed department.

It is important to understand that while virtually all C programs can be converted to an electronic circuit by the C-to-Hardware Compiler, it is the characteristics of a source function that ultimately determines whether the Compiler can create an efficient hardware component, or whether it is better to execute that function on a processor core. The Compiler can only create a small and fast electronic circuit if the C source code is parallelizable.

Providing Hardware Acceleration

Choosing Functions to Implement in Hardware

Generation and use of Hardware Functions