Mismatching Address or Data Widths of OpenBus Ports

This compiler hint appears when an OpenBus Link has been placed between the Master and Slave ports of two OpenBus components, and those ports have differing widths for their constituent address and/or data buses. The message is displayed in the Messages panel in the following format:

Address/data width of slave port PortName1 (ComponentName1) doesn't match address/data width of master port PortName2 (ComponentName2),

where

PortName1 is the name of the Slave port to which the link is connected (e.g. s0)

ComponentName1 is the designator of the parent component to which the Slave port is associated

PortName2 is the name of the Master port to which the link is connected (e.g. m0)

ComponentName2 is the designator of the parent component to which the Master port is associated.

Default Report Mode

Fatal Error

Recommendation

This situation can arise for example if you connect a peripheral with an 8-bit data bus directly to the IO port of a processor, which has a 32-bit data bus. In such a system, delete the link between the processor and the peripheral, and place an Interconnect component in-between. The Interconnect will handle connection of the different data buses and also streamline the addressing – taking the 24-bit address line from the processor and mapping it to the n-bit address line used to drive the peripheral device.

On the memory side, a single physical memory device of any address width can be connected directly to the processor's MEM port. This port is 32-bits wide for both address and data – if memory is connected with a lower address width, the system will essentially just ignore the upper bits that aren't used.