Forbidden OpenBus Link

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Modified by Phil Loughhead on Feb 20, 2014

This compiler hint appears when an OpenBus Link has been placed, invalidly, to effect connection of two Interconnect or Arbiter components in a cascaded fashion. Note that when placing links, you will automatically be prevented from linking two Master or two Slave ports together. The message is displayed in the Messages panel in the following format:

Forbidden link between slave port PortName1 (ComponentName1) and master port PortName2 (ComponentName2),

where

PortName1 is the name of the Slave port to which the offending link is connected (e.g. s0)

ComponentName1 is the designator of the parent Interconnect or Arbiter component to which the Slave port is associated

PortName2 is the name of the Master port to which the offending link is connected (e.g. m0)

ComponentName2 is the designator of the parent Interconnect or Arbiter component to which the Master port is associated.

Default Report Mode

Fatal Error

Recommendation

Ensure that two Interconnect or Arbiter components are not linked together (cascaded) in your OpenBus System. Typically, there will be just two Interconnect components in a single processor system, one linked to the processor's IO port and the other linked to the processor's MEM port. If you have used more than one Interconnect component on either the slave memory or peripheral I/O sides of the system, simply delete the additional Interconnect component(s) and re-link the desired peripherals accordingly.

Similarly, Arbiter components in an OpenBus System containing a single processor will typically be used to provide shared access to physical memory devices. Depending on the intended use of the memory, the system may contain a single Arbiter – providing access to a single memory or bank of memories between the processor and one or more memory-based peripherals – or several Arbiters – if certain memory-based peripherals are to share access with the processor of one type of memory (e.g. EMAC RAM), and others are to share access with the processor of another type of memory (e.g. Video RAM).