Conflicting Constraints

Old Content - visit altium.com/documentation

Modified by Phil Loughhead on Feb 20, 2014

This compiler hint appears when a configuration contains at least two constraints targeting the same top-level port in an FPGA design, and those constraints are mapping the port to different pins of the target physical device. The message is displayed in the Messages panel in the following format:

Port PortName FPGA_PINNUM Constraints Pin1 And Pin2 Conflict in ConfigurationName,

where

PortName is the name of the top-level port in the design. In an associated constraint file, this entry is the value assigned to the TargetId field of the corresponding constraint record

Pin1 is the value assigned to the FPGA_PINNUM field for the targeted port in a constraint file associated to the configuration

Pin2 is the value assigned to the FPGA_PINNUM field for the same targeted port in an additional constraint file associated to the configuration

ConfigurationName is the name of the offending configuration.

Default Report Mode

Error

Recommendation

Use the Compile Errors dialog to cross probe quickly to the offending constraints. Decide which of the duplicate constraints are redundant to the design and delete them accordingly. The pin number assignments for ports will typically be kept within a single constraint file. If a duplicate constraint resides in another constraint file, it is highly likely to be an erroneous entry.

If the duplicate constraint entries reside in the main constrain file (for pin mappings) and you are unsure which constraint is the right one to keep, you can simply:

Delete all the Port-related constraints in the file
Run the Design » Import Port Constraints from Project command - to add a constraint for each port in the FPGA project.
Run the Place and Route tools (Build stage in the associated Process Flow) and then import the pin assignments back into the constraint file.