Cascaded Interconnects In Openbus Document

This compiler hint appears when the Master port of one Interconnect component is linked to the Slave port of another Interconnect component, thereby forming a cascade of Interconnect components in the OpenBus System. The message is displayed in the Messages panel in the following format:

Cascaded interconnects InterconnectName1 and InterconnectName2,

where

InterconnectName1 is the designator of the first offending Interconnect component

InterconnectName2 is the designator of the second offending Interconnect component

Default Report Mode

Fatal Error

Recommendation

Ensure that two Interconnect components are not linked together in your OpenBus System. Typically, there will be just two Interconnect components in a single processor system, one linked to the processor's IO port and the other linked to the processor's MEM port. If you have used more than one Interconnect component on either the slave memory or peripheral I/O sides of the system, simply delete the additional Interconnect component(s) and re-link the desired peripherals accordingly.