Adding Hidden Net to Sheet

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Modified by Phil Loughhead on Feb 20, 2014

This compiler hint is related to multi-part components and appears when you have specified one or more pins to be hidden and connected to an existing net within the design - typically a power pin connected to VCC or GND for example. The message is displayed in the Messages panel in the following format:

Adding hidden net

Default Report Mode

Warning

Recommendation

The problem arises when the following properties for the offending pin(s) are evident (in the associated Pin Properties dialog):

The Hide option is enabled
The Connect To field contains the specific power net name
The Part Number is that of the placed part (i.e. other than 0).

To resolve this issue, you could enable the display of the pin(s) in the workspace (simply disable the Hide option). This option may prove to be less than desirable, especially if you have many hidden pins connected to power nets. Revealing these pins in the workspace can cause clutter as each pin would need to be wired to the appropriate power port object - preventing the design schematic(s) from being easily read.

A better solution is to clear the Connect To field and set the Part Number field to 0. Leave the Hide option for the pin enabled. Repeat for each pin that has been connected to a power net in this way. Ideally, the power net connections should be assigned through use of part 0 in the source library component.

Notes

Only one instance of this violation type will be listed in the Messages panel. When investigating the error using the Compile Errors panel, a single entry will be listed reflecting the net which is being added. There may be multiple nets added - such as GND and VCC - but only one will be listed, determined by alphabetical order. If you clear the violation for a particular net, the next net (in order) will appear under this violation type.