Run SI

The following content has been imported from Legacy Help systems and is in the process of being checked for accuracy.

Parent process: WorkspaceManager:ProjectSpecificProcess

Applied parameters: Server=SignalIntegrity|Command=RunStandardTests|ProjectKind=PCBProject

Summary

This command is used to perform a signal integrity analysis of the current design.

Details

After launching the command, an analysis of the current board will be carried out and any errors or warnings will be flagged by the appearance of the Errors or warnings found dialog. If this dialog does appear, you will be given the option to either continue with the analysis or cancel it.

All errors/warnings will be listed in the Messages panel. It is a good idea to fix any conditions that are causing these, as they could create further problems at a later stage when using the Signal Integrity Analyzer.

A common source of generated warnings lies in the non-assignment of Signal Integrity models with respect to all components in the design. The Errors or warnings found dialog carries a third button - Model Assignments - which opens the Signal Integrity Model Assignments dialog, from where you can view and edit the model assignments for all design components.

If no warnings are present, if you click Continue in the Errors or warnings found dialog, or if you click Analyze Design in the Signal Integrity Model Assignments dialog, the analysis will proceed.

If you are running an analysis on the design for the first time, the SI Setup Options dialog will appear. This dialog allows you to define values for Track Impedance and Average Track Length. The former will be used when there are nets that have not yet been transferred to the PCB. The latter will be used for unrouted nets that have been transferred to the PCB, in addition to defined routing width/impedance rules.

If unrouted nets exist in the PCB, but the components for the design have been placed, then enabling the Use Manhattan length will ensure that the Manhattan length is used in the analysis calculations.

When the routing characteristic setup options are defined as required, click the Analyze Design button.

An initial, default screening analysis will be performed, using default overshoot/undershoot rules and any user-defined signal integrity design rules. The Signal Integrity panel will appear, listing the results of this initial analysis.

Each net will be given one of three possible status settings:

Passed (green block)- all values within specified tolerance level for each of the defined rules.

Failed (red block)- at least one value outside specified tolerance level for one or more of the defined rules (entry associated with violated rule is shaded pale red in color).

Not Analyzed (orange block)- net unable to be screened.

Any nets that fail the screening analysis and contain errors that will cause them to fail reflection and/or crosstalk analyses will appear with their entire row entry colored in bright red.

Any nets that are unrouted in the PCB will appear with their entire row entry colored in light grey.

Use the main screening analysis area of the panel to quickly identify problem nets in the design. These nets can then be investigated in greater depth using the Reflection and Crosstalk analyses.

Probably the best characteristics to use in determining which nets may be the most problematic, are overshoot and undershoot.

As you run a reflection or crosstalk analyses, a simulation waveform file (ProjectName.sdf) will be generated, appear in the Projects panel under the Generated SimView Data Files folder and open as a separate tab in the main design window, to display the results of the analyses in the Simulation Data Viewer's Waveform Analysis window.

Notes

If errors are present in the design that prevent signal integrity analysis, the analysis will be aborted. Instead, you will be alerted to the fact that errors exist. These errors can be viewed in the Messages panel.

Although each net can be screened to provide net and impedance data, not all nets can be analyzed for signal integrity characteristics (voltage and timing). In order to screen successfully for all characteristics, a net must contain at least one IC with an output pin and no other components. Resistors, capacitors and inductors will not simulate for example, because of their lack of output pin to provide a driving source. It should be noted that when bi-directional nets are screened, both directions are simulated and the worst case result is displayed.

In order to run a successful signal integrity analysis of the design and obtain accurate results, the following has to be performed:

The associated signal integrity model type for each component has to be correct. This is achieved by setting the correct entry for the Type field in the Signal Integrity Model dialog, when editing the SI model associated to the component placed on the schematic source document. If this entry is not defined, the type Integrated Circuit will be assumed.

A Signal Stimulus design rule must be set up. By default, no rule exists and the settings associated when creating a new rule of this type are assumed.

There must be Supply Nets design rules. Generally there should be at least two rules, one for power nets and one for ground nets. The scope for these can be either net or net class.

The layer stack must be setup correctly. The Signal Integrity tool requires continuous power planes (split planes are not supported, the net that is assigned to the plane is used). If they are not present they are assumed, so it is far better to add them and set them up appropriately. The thickness of all Layers, Cores and Prepreg must be set correctly for the board.