The following content has been imported from Legacy Help systems and is in the process of being checked for accuracy.
Parent process: WorkspaceManager:ProjectSpecificProcess
Applied parameters: ProjectKind=FPGAProject,CoreProject|Server=EditVHDL|Command=SynthesizeProject
Summary
This command is used to synthesize the active project, taking and translating the VHDL source documents to ultimately produce an EDIF netlist, optimized and ready for placement and routing into an FPGA.
Details
First, ensure that one of the source documents associated with the project that you wish to synthesize, is the active document in the main design window. Then launch the command.
Any schematic documents are first translated into corresponding VHDL documents, in the format
SchematicDocumentName.vhd. The VHDL Synthesizer then analyses the design to verify that its statements are syntactically correct and synthesizable, determines the logic necessary to create an equivalent netlist and then generates that netlist. Synthesis is carried out in accordance with the options defined in the
Synthesis tab of the
VHDL Project Options dialog.
The netlist (
ProjectName.EDN) is generated in the output folder and added to the
Projects panel under the
Generated EDIF Documents sub-folder. The document is initially closed.
Notes
The output path for generated files is set in the
Options tab of the
Options for Project dialog. By default, the output path is set to a sub-folder under the folder that contains the Project file and has the name:
ProjectOutputs. The output path can be changed as required.
If any warnings are encountered during synthesis, the first warning will be cross-probed to upon synthesis completion, with the offending source document opened as the active document in the main design window.
If any errors are encountered that prevent synthesis, then the EDIF netlist will not be generated. A log file (
VHDLtoEDIF.log) can be interrogated to see the actions that occurred during the synthesis operation and can prove a useful source of information for both a successful and unsuccessful synthesis.
Select a warning or error message related to synthesis in the
Messages panel and press
F1, to link to a help topic detailing the warning/error.