Simulate Project

The following content has been imported from Legacy Help systems and is in the process of being checked for accuracy.

Parent process: WorkspaceManager:ProjectSpecificProcess

Applied parameters: ProjectKind=FPGAProject,CoreProject|Server=EditVHDL|Command=SimulateProject

Summary

This command is used to run a simulation for the active project.

Details

First, ensure that one of the source documents associated with the project that you wish to simulate, is the active document in the main design window. Then launch the command.

The source documents for the active project are firstly compiled. Each source VHDL document (*.VHD) and VHDL testbench (*.VHDTST) are passed through the Analyzer, producing the intermediate analyzed files (*.AN).

If there are source schematic documents in the project, each schematic is translated into VHDL - creating a corresponding VHDL document which is then analyzed to provide the .AN file. These files are added to the Projects panel under the Generated VHDL Documents sub-folder.

The intermediate analyzed files are then passed to the Elaborator, where they are linked together to produce an elaborated file (*.DP). This, in turn, is used to generate the simulation executable file (*.VX).

With the analyzing, elaboration and generation phases complete and all required files generated, the VHDL Simulator is started. A digital wave file (ProjectName.SO) is created, added to the Projects panel under the Generated Digital Wave Files sub-folder and opened as the active document in the main design window. If you have enabled the Show execution point option in the Debugging Options region of the VHDL Preferences dialog, the generated VHDL document for the top-level schematic in the design will be opened as the active document, with the next executable line of VHDL code highlighted.

The Edit Simulation Signals dialog also appears. This dialog basically lists all of the signals in the design, in terms of blocks. The top block (with no name) represents the top-level signals contained in the testbench (Which equate to the ports of the top-level schematic document, where one exists). Each block that follows represents the signals local to a component instantiation within the design.

The dialog offers you control over which signals are enabled for simulation (whether data is to be collected for them) and which of these enabled signals are also chosen to be displayed graphically in the Waveform Viewer. Enable/disable signals as required - top-level signals are, by default, all enabled for simulation and waveform display - and click the Done button when finished.

As mentioned previously, the VHDL Simulator is started using this command, but the actual simulation does not proceed automatically. To start the simulation, you need to use one of the various run or step commands.

Notes

The output path for generated files is set in the Options tab of the Options for Project dialog. By default, the output path is set to a sub-folder under the folder that contains the Project file and has the name: ProjectOutputs. The output path can be changed as required.

The output folder will also contain a library file (*.AL). This is the internal simulator project library file and can be equated to the Work library. It basically contains the entity-architecture pairings that are found in each of the VHDL source documents.

Any VHDL Library documents that are part of the project will also be compiled. The constituent VHDL documents of a library document will be compiled if they have been enabled for simulation.

If you have multiple testbenches in your project, all will be compiled to produce the intermediate analyzed files (*.AN). However, only the testbench document whose entity is declared as the top-level entity, in the Simulation tab of the VHDL Project Options dialog, will be used by the Elaborator to ultimately produce the simulation executable file (*.VX).

Testbenches must be placed at the top of the ordered documents list in the Design Documents tab of the VHDL Project Options dialog, in order for correct compilation to occur. This is because compilation order is from the bottom-up, with the low-level VHDL documents being compiled first.

Select a warning or error message related to simulation in the Messages panel and press F1, to link to a help topic detailing the warning/error.