FPGA Workspace Map

The following content has been imported from Legacy Help systems and is in the process of being checked for accuracy.

Parent process: WorkspaceManager:FPGAWorkspace

Applied parameters: None

Summary

This command is used to run the FPGA Workspace Map dialog, from where you can check the status of linking between FPGA and PCB projects and pass design changes between linked elements in order to maintain synchronicity.

After launching the command, the FPGA Workspace Map dialog will appear. The dialog displays the relationships (links) between various elements of FPGA and PCB projects and the status of these links - whether the two sides of a link are synchronized and up-to-date or whether some action is required to resynchronize them.

The various elements in the two project types are linked in a logical flow - from a soft core microcontroller placed within an FPGA project, to a PCB design document within a linked PCB project. Each of the links are summarized as follows:

FPGA Project - Soft Processor

The Soft Processors region of the dialog is purely added for completeness and offers at-a-glance information on the core microcontroller(s) that are being used in a particular FPGA project. The link, as such, is therefore cosmetic. It will always be displayed as synchronized.

Schematic Document (PCB Project) - FPGA Project

This link reflects the synchronized status between the FPGA Component in the PCB project and the appropriate configuration in the FPGA project. When determining the status, the software is looking for any net-related changes.

PCB Document - Schematic Document (PCB Project)

This link reflects the synchronized status between the FPGA Component footprint on the PCB document and the FPGA Component symbol on the schematic sheet, both within the PCB project.

A link can appear in one of two colors and hovering over a link will produce a textual description of its status:

The Green link signifies up to date (i.e. both sides are synchronized). No action is required.

The Red link signifies that the two sides of the link are not fully synchronized (i.e. a design change has been made on one side but has yet to be passed to the other). Clicking on a Schematic-FPGA Project link with this status will open the Synchronize dialog, from where you can browse and match any unmatched ports and pins.

When two elements of the map are shown to be un-synchronized (i.e. the link between them is red), clicking on the link or its associated icons will give access to a number of synchronization options. The hint that appears when hovering over the link will, where possible, provide information on which directions updates should be made in order to achieve synchronization.

Before passing on any design changes over a link, you can view the differences. Changes are made using Engineering Change Orders (ECOs)

Notes

Entries in the schematic and/or PCB regions of the PCB project will appear if they contain recognized and supported FPGA components. However, the Schematic-FPGA Project link will only appear if the FPGA project has been linked to the PCB project.

For more detailed information about linking FPGA and PCB projects, and how to use the FPGA Workspace Map dialog to pass design changes between the two, refer to the application note 'Linking an FPGA Project to a PCB Project', which can be found in the FPGA Design section of the Online Help system.