Create Verilog File From Sheet Symbol

Old Content - visit altium.com/documentation

Modified by Admin on Nov 6, 2013

Parent process: Sch:CreateSheetFromSheetSymbol

Applied parameters: DocumentKind=Verilog

Summary

This command is used to create a new Verilog document from a sheet symbol on the current schematic document. In this way, you can automatically create Verilog sub-modules for each of the sub-sheets of a multi-sheet schematic design, based on the sheet symbols you have created and placed on the top sheet.

First, ensure that the schematic sheet that contains the sheet symbol(s) is the active document in the main design window.

After launching the command, the cursor will change to a crosshair and you will be prompted to choose a sheet symbol. Simply position the cursor over the sheet symbol that you wish to create a Verilog document from and click or press ENTER. The Verilog document will be created and opened as the active document. The sheet entries on the symbol will be included in the module's definition.

Availability

In Sch Editor, run command Design >> Create HDL File From Sheet Symbol >> Create Verilog File From Sheet Symbol.