Add Stitching to Net

Parent page:  PCB Dialogs

Summary

Via stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure, helping maintain a low impedance and short return loops. In RF designs stitching is used in combination with guard rings to create a via wall, helping create an electromagnetically 'quiet' PCB. Via stitching can also be used to tie areas of copper that might otherwise be isolated from their net, to that net.

The Add Via Stitching to Net dialog allows the designer to configure stitching settings for the design, including stitching parameters and via style. Via stitching is run as a post-process, filling free areas of copper with stitching vias. For via stitching to occur, there must be overlapping regions of copper that are attached to the specified net, on different layers. Supported regions of copper include Fills, Polygons and Power Planes.

Using the selected net, the stitching algorithm identifies all Fills, Polygons and Power Planes attached to that net and attempts to connect them through the board, using the specified via and stitching pattern.  

The via stitching algorithm treats Polygons, Fills and Planes in the following way:

1. Polygons and Fills that are on the same net are stitched wherever they overlap on different layers. If there are Polygons or Fills on other nets that are overlapping within that area (on another layer), stitching is not applied in that region. Overlapping Plane regions on other nets are passed through.
2. Overlapping Plane regions on the target net are always stitched, regardless of the presence of Plane regions (on another layer) attached to other nets. Rule 1 above applies if there are Polygons or Fills overlapping in the same region.

Access

In PCB Editor, run command Tools » Via Stitching » Add Stitching to Net.

Options/Controls

Stitching Parameters

The stitching parameters control the stitching vias' placement pattern, and their clearance from other-net and same-net objects.

• Net - Select the Net to be used for stitching first as this effects the behavior of other options, such as clicking the Load values from Routing Via Style Rule button.
• Grid - the distance between the center of adjacent stitching vias. Stitching vias will not be placed in violation of applicable design rules, if a potential via site would result in a violation that site is skipped.    
• Constrain Area - Enable the Constrain Area checkbox to constrain via stitching to a specific area, 
• Edit Area - Click this button to edit the constrain area.
• Stagger alternate rows - alternate rows of stitching vias are offset by half of the Grid value.  

Same Net Clearances

There are 2 ways of controlling the clearance of stitching vias, to vias and pads on the same net. Either the applicable Clearance design rule is used, or the Default Via/Pad Clearance specified here in the dialog is used. If a rule exists, then the tighter of these 2 settings is used. These options behave as follows:

• Default Via/Pad Clearance - stitching vias are only placed on potential stitching sites if this much clearance exists. Since potential stitching sites are determined by the stitching grid, it is likely they will be further than apart than this setting.  
• Create New Clearance Rule - a stitching via -versus- other via/pad design rule is created when this button is clicked. This rule setting is used to ensure a potential stitching site is valid. When the button is clicked the PCB Rules and Constraints Editor opens, so that the rule Constraints can be set. Note that the rule is named and scoped to target the net selected in the Add Stitching to Net dialog.  
• Edit Clearance Rule - this will be the button text if an applicable design rule already exists. Click to change the rule Constraint settings. 
• Min Boundary Clearance - stitching vias are only placed on potential stitching sites if this much clearance exists to the edge of Polygon/Fill/Plane regions. 

The clearance from a stitching via to objects on other nets is controlled by the applicable clearance design rule. A stitching via will not be placed on a potential stitching site if it will violate the applicable design rule.

Via Style

The stitching Via Style can be configured manually in the Add Stitching to Net dialog, or imported from the applicable Routing Via Style design rule by clicking the Load values from Routing Via Style Rule button. Clicking this button will load the Preferred rule settings. 

Diameters

• Simple - Via Style(Hole size and diameter) is the same through all layers.
  
  • Hole size - Specify the hole size value for the Via.
  • Diameter - Specify the diameter for the Via.

• Top-Middle-Bottom - Different Hole Size and Diameters can be set at Top Layer, Middle Layer and Bottom Layer respectively.
  
  • Hole size - Specify the hole size value for the Via.
  • Top Layer - Specify via size for top layer.
  • Middle Layer - Specify via size for Middle layer.
  • Bottom Layer - Specify via size for Bottom layer.

• Full Stack - Different Hole Size and Diameters can be edited at each layer(including all signal layers and planes).
  
  • Hole size - Specify the hole size value for the Via.
  • Edit Full Stack Via Sizes - Click to open Via Layer Editor dialog, in which to specify via settings for each layer stack.

Properties

• Start Layer - Specify the start layer of the via.
• End Layer - Specify the end layer of the via.

Solder Mask Expansions

• Expansion value from rules - Enable this option to allow the existing solder mask expansion rule to take effect on this pad object. Check the Mask design category from the PCB Rules and Constraints Editor dialog.
• Specify expansion value - Enable this Specify expansion value option to edit the expansion value and the solder mask expansion design rule is overridden for this pad.

• Force complete tenting on top - Enable the Force complete tenting on top option and any solder mask settings in the solder mask expansion design rules will be overridden and results in no opening in the solder mask on top layer of this pad. 
  Disable this option and this pad is affected by a solder mask expansion rule or specific expansion value.

• Force complete tenting on bottom - Enable the Force complete tenting on bottom option and any solder mask settings in the solder mask expansion design rules will be overridden and results in no opening in the solder mask on the bottom layer of this pad. 
  Disable this option and this pad is affected by a solder mask expansion rule or specific expansion value. 

Notes

• Once stitching is complete, you will need to re-pour the polygons if the applicable Polygon Connect Style design rule specifies a relief connection style.
• Each set of stitching vias are added to a union. The set can be removed by running the Tools » Via Stitching » Remove Via Stitching Group command, then clicking on any via in the group.