Add Port Constraints

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Modified by Admin on Mar 11, 2014

Parent process: EditConstraints:AddConstraint

Applied parameters: Type=Port

Summary

This command is used to add constraint groups targeting each of the ports on the top-level schematic sheet of the parent FPGA design project.

Availability

In the constraint document, run the commmand Design » Import Port Constraints from Project.

Details

After launching the command, Port constraint groups will be entered for the top-level schematic ports of the FPGA design. Each constraint group will target a port in the design (as shown in the example below), but no specific constraint kinds or values will be entered.

Record=Constraint | TargetKind=Port | TargetId=CLK_BRD

Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK

Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TDI

Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TDO

Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TMS

Record=Constraint | TargetKind=Port | TargetId=LEDS[7..0]

Record=Constraint | TargetKind=Port | TargetId=SPEAKER

Record=Constraint | TargetKind=Port | TargetId=TEST_BUTTON

Notes

To modify a Port constraint group, either type directly within the constraint file, or use the corresponding Add/Modify Constraint sub-command from the Design menu.