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Configuring the Logic Analyzer
... device. This input will have the default name Set0_Spare n-1..0 , where n is the Capture Width. The figure above shows the default ...
admin - 09/13/2017 - 15:32
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ESRC - Voltage-Controlled Voltage Source Model
Model Kind Voltage Source Model Sub-Kind Voltage-Controlled SPICE Prefix E SPICE Netlist Template Format @DESIGNATOR %3 %4 %1 %2 @GAIN Parameters (definable at component level) The followi...
phil.loughhead@... - 03/04/2014 - 00:51
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ESRC - Voltage-Controlled Voltage Source Model
Model Kind Voltage Source Model Sub-Kind Voltage-Controlled SPICE Prefix E SPICE Netlist Template Format @DESIGNATOR %3 %4 %1 %2 @GAIN Parameters (definable at component level) The followi...
admin - 09/13/2017 - 15:32
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FSRC - Current-Controlled Current Source Model
Model Kind Current Source Model Sub-Kind Current-Controlled SPICE Prefix F SPICE Netlist Template Format V@DESIGNATOR %1 %2 0V @DESIGNATOR %3 %4 V@DESIGNATOR @GAIN Parameters (definab...
phil.loughhead@... - 03/04/2014 - 00:51
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FSRC - Current-Controlled Current Source Model
Model Kind Current Source Model Sub-Kind Current-Controlled SPICE Prefix F SPICE Netlist Template Format V@DESIGNATOR %1 %2 0V @DESIGNATOR %3 %4 V@DESIGNATOR @GAIN Parameters (definab...
admin - 09/13/2017 - 15:32
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HSRC - Current-Controlled Voltage Source Model
Model Kind Voltage Source Model Sub-Kind Current-Controlled SPICE Prefix H SPICE Netlist Template Format V@DESIGNATOR %1 %2 0V @DESIGNATOR %3 %4 V@DESIGNATOR @GAIN Parameters (definab...
phil.loughhead@... - 03/04/2014 - 00:51
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HSRC - Current-Controlled Voltage Source Model
Model Kind Voltage Source Model Sub-Kind Current-Controlled SPICE Prefix H SPICE Netlist Template Format V@DESIGNATOR %1 %2 0V @DESIGNATOR %3 %4 V@DESIGNATOR @GAIN Parameters (definab...
admin - 09/13/2017 - 15:32
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Configuring the Logic Analyzer
... device. This input will have the default name Set0_Spare n-1..0 , where n is the Capture Width. The figure above shows the default ...
admin - 11/06/2013 - 09:09