Release notes for Altium Designer 10 update (10.818.23272)

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Modified by Admin on Dec 5, 2013

Additional Resources

Complete list of Altium Designer updates

Update 15: Updated plug-ins from release 10.771.23139 to 10.818.23272

Date: 19 December 2011

Key highlights

Custom pad shapes

As a result of the very first BugCrunch report that was voted in, this latest update adds the ability to add solder and paste mask expansion rules to regions, fills, and tracks. So now you can attach virtually any copper geometry to a pad and give it ‘pad-like’ solder and/or paste mask expansions. More information. View BugCrunch report #67.

Loop removal improvements

The Advanced Interactive Router's loop remove algorithm has been improved which will fix a variety of known issues as well as deliver better overall results. View BugCrunch report #132. View BugCrunch report #425. View BugCrunch report #596.

Print from PCB Library

This was the second issue to get voted through in BugCrunch and also very popular. So we've implemented the request and footprints can now be printed directly from a PCB library. View BugCrunch report #109.

Designators movable by multiple selections in PCB

Again, a popular item in BugCrunch. So, moving multiple component designators is now supported in PCB using the Move>>Selection command. View BugCrunch report #1089.

Additional FPGA Vendor Constraints and Device Support

This update includes added support for Altera’s Max V and Stratix IV CPLD/FPGA devices. In addition to this, Altium Designer’s constraint files have been significantly revamped to include support for a large array of extra Vendor constraints. This will let you continue creating vendor-neutral FPGA designs using the latest IO standards from within Altium’s Unified Design Environment.

Proxy scripts supported

If you have had problems previously with installing and updating AD10 because of access through proxy servers, we’ve implemented a couple of fixes that should now resolve those issues. Instructions for deploying improved proxy support. View BugCrunch report #103.

The new Altium Installer and Download Manager require Internet Explorer 7 or later to be installed on your PC. If you have earlier versions, or do not have it installed, you will not be able to install successfully, or to update after this release.

System Components: Altium Designer Base

5709	FPGA Signal Manager has been improved. IO Standard constraints are correctly translated to Altium Constraint file.
5794	The issue causing blank pdf pages in schematic outputs under certain circumstances has been fixed.

System Components: Altium Designer Installation System

4437	AltiumInstaller and AltiumDownloadManager are updated with improved Proxy support. Proxy server settings must be configured in Internet Explorer's Internet Options > Connections > LAN Settings. Manual proxy sign-ins are not supported. Instructions for deploying improved proxy support.
4438	AltiumInstaller and AltiumDownloadManager have improved support for automatic configuration script files setup in Internet Explorer's Internet Options. Instructions for deploying improved proxy support. View BugCrunch report #103.

System Components: Data Management

5781	Changed warning displayed during connection to Vault dialog to be based on license subscription instead of AltiumLive plan.

System Components: PCB System

3565	Fixed PCB problem where Y coordinate of custom board origin and dimensions was reset if Hungarian Locale was used. View BugCrunch report #673.
3567	Resolved Paste Special issue of multiple nets on different layer
4452	Footprints can now be printed from a PCB library. View BugCrunch report #109.
4794	Fixed the Advanced Interactive Router to properly handle room specific clearance rules when in Walkaround Obstacles mode.
5329	TANGO ASCII file format importer will now work as expected.
5401	Added loop remove shortcut (Shift-D) to the Advanced Interactive Routers. View BugCrunch report #596.
5539	Non pad primitives have been given the applity to generate mask layer expansions when they are on the top or bottom layers. This will simplify the creation of complex pad shapes. More information. View BugCrunch report #67.
5543	Fixed a variety of problems with Advanced Interactive Router's loop remove algorithm. View BugCrunch report #132. View BugCrunch report #425.
5722	Fixed PCB crash when deleting component with .Designator special string which was in violation with another silkscreen object.
5752	Moving multiple component designators is now supported in PCB using the Move>>Selection command. View BugCrunch report #1089.

System Components: Schematic System

5679	Fixed slowness experience by some users on copy. View BugCrunch report #1182.
5793	Tabbed text in text frames is now rendered correctly with Render text with gdi+ option on.

System Components: Soft Design Support

2598	A parameterized blackbox module is instantiated correctly also if the blackbox is instantiated multiple times where each instantiation assigns a different value, or the default value. I.e. the different parameter values are stored in the EDIF file.
4426	Altium Core Generator has been improved. Internal block memory supports hex file initialization for memories larger than 64K.
4622	Unisim library support updated, now compatible with Xilinx V13.3.
4904	An incorrect VHDL condition with OTHERS could cause a failed assertion and then an access violation
5098	Altera Stratix 4 device support has been added to Altium Designer.
5606	Altera Max 5 device support has been added to Altium Designer.
5666	SSTL15I IO standard is translated to Altera "SSTL-15 CLASS I" constraint.
5667	SSTL15II IO standard is translated to Altera "SSTL-15 CLASS II" constraint.
5668	DSSTL15I IO standard is translated to Altera "DIFFERENTIAL 1.5-V SSTL CLASS I" constraint.
5669	DSSTL15II IO standard is translated to Altera "DIFFERENTIAL 1.5-V SSTL CLASS II" constraint.
5671	Altera Stratix 3 IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5672	Altera Stratix 2GX IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5675	Altera Stratix 4 IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5676	Altera Max 5 IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5710	Add/Modify Port Constraint dialog has been updated. IO Standards use descriptive names for display in combo box.
5711	Altera pin file importer has been improved. 3.3V LVCMOS and LVTTL iostandards are imported correctly.

System Components: Soft Design Synthesis Libraries

4622	Unisim library support updated, now compatible with Xilinx V13.3.

System Components: Soft Design System

2598	A parameterized blackbox module is instantiated correctly also if the blackbox is instantiated multiple times where each instantiation assigns a different value, or the default value. I.e. the different parameter values are stored in the EDIF file.
4622	Unisim library support updated, now compatible with Xilinx V13.3.
4904	An incorrect VHDL condition with OTHERS could cause a failed assertion and then an access violation
5098	Altera Stratix 4 device support has been added to Altium Designer.
5425	Core Project outputs handling has been improved. Vhdl macrocell outputs from Altium Synthesizer are copied across to linked fpga project. View BugCrunch report #791.
5436	FPGA_CLOCK constraint handling has been improved when XST synthesizer is used.
5437	FPGA_CLOCK_PIN constraint handling has been improved when XST synthesizer is used.
5438	FPGA_CLOCK constraint handling has been improved when XST synthesizer is used. When set to FALSE it will prevent XST from using clock buffer on object it has been applied to.
5439	FPGA_CLOCK_PIN constraint handling has been improved. When used with XST synthesizer and set to False it will prevent XST from inserting ibufg primitive on port it has been applied to.
5440	FPGA_CLOCK constraint handling has been improved. When used with Quartus synthesizer and set to True it will enforce Quartus to use global buffer.
5441	FPGA_CLOCK constraint handling has been improved. When set to False and used with Quartus synthesizer it will prevent usage of global buffer.
5447	FPGA_CLOCK constraint handling has been improved. When used with Synplify will enforce global clock buffer insertion.
5448	FPGA_CLOCK_PIN constraint handling has been improved. When used with Synplify synthesizer will enforce clock buffer usage.
5449	FPGA_CLOCK constraint handling has been improved. When set to False and used with Synplify synthesizer it will prevent global buffer insertion.
5450	FPGA_CLOCK_PIN constraint handling has been improved. When set to False and used with Synplify it will prevent synthesizer from using global clock buffer.
5471	FPGA_CLOCK_FREQUENCY constraint handling has been improved. When used with Synplify synthesizer it will request timing based synthesis. Applies to standalone, Actel and Lattice version.
5473	Xilinx Bit Generation build step has been improved. Bitgen DRC is run against design autogenerated pcf constraint.
5496	Linking Core project to FPGA project no longer requires device specific configuration for the core project to build them without publishing.
5505	FPGA_CLOCK_FREQUENCY constraint is correctly handled when used with Synplify targeting Actel devices.
5507	FPGA_CLOCK_FREQUENCY constraint handling for Actel devices has been improved. Net objects are handled correctly.
5606	Altera Max 5 device support has been added to Altium Designer.
5608	When unsupported IO standard is applied in Altium constraint file to Altera target Altium Designer will issue warning.

FPGA Components: FPGA Configurable - Generic Logic

5098	Altera Stratix 4 device support has been added to Altium Designer.
5606	Altera Max 5 device support has been added to Altium Designer.

FPGA Components: FPGA Configurable - Wishbone Memory Controller

5498	Shared USB controller template has been improved. Wishbone acknowledge line is asserted for single clock cycle only.

FPGA Design Tools: Ancillary VHDL Synthesis Libraries

5610	DHSTL18I IO Standard is mapped to Altera "DIFFERENTIAL 1.8-V HSTL CLASS I" constraint.
5611	DHSTL18II IO standard is mapped to Altera "DIFFERENTIAL 1.8V HSTL CLASS II" constraint.
5612	DHSTLI IO Standard is translated to Altera "DIFFERENTIAL 1.5-V HSTL CLASS I" constraint.
5613	DHSTLII IO standard is translated to Altera "DIFFERENTIAL 1.5-V HSTL CLASS II" constraint.
5614	LVCMOS12 IO standard is translated to Altera "1.2 V" constraint.
5615	BLVDS25 IO standard is translated to Altera "BUS LVDS" constraint.
5616	LVDS_E_3R IO standard is translated to Altera "LVDS_E_3R" constraint.
5617	LVDS_E_1R IO standard is translated to Altera "LVDS_E_1R" constraint.
5618	MINILVDS25_E_1R IO standard is translated to Altera "MINI-LVDS_E_1R" constraint.
5619	MINILVDS25_E_3R IO standard translates to Altera "MINI-LVDS_E_3R" constraint.
5620	RSDS25_E_1R IO standard translates to Altera "RSDS_E_1R" constraint.
5621	RSDS25_E_3R IO standard translates to Altera "RSDS_E_3R" constraint.
5622	LVTTL12 IO standard translates to Altera "1.2 V" constraint.
5623	RSDS33 IO standard translates to Altera "RSDS" constraint.
5624	LVCMOS30 IO standard translates to Altera "3.0-V LVCMOS" constraint.
5625	LVTTL30 IO standard translates to Altera "3.0-V LVTTL" constraint.
5626	PCML12 IO standard translates to Altera "1.2-V PCML" constraint.
5627	PCML14 IO standard translates to Altera "1.4-V PCML" constraint.
5628	PCML25 IO standard translates to Altera "2.5-V PCML" constraint.
5629	HCSL IO Standard translates to Altera "HCSL" constraint.
5630	PCI33_30 IO standard is translated to Altera "3.0-V PCI" constraint.
5631	PCIX_30 IO standard is translated to Altera "3.0-V PCI-X" constraint.
5632	PPDS25 IO standard is translated to Altera "PPDS" constraint.
5633	PPDS25_E_3R IO standard is translated to Altera "PPDS_E_3R" constraint.
5634	BLVDS33 IO standard is translated to Altera "BUS LVDS" constraint.
5635	Altera ArriaGX IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5644	Altera Cyclone IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5646	Altera Cyclone2 IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5648	DHSTL12I IO standard is translated to Altera "DIFFERENTIAL 1.2-V HSTL CLASS I" constraint.
5649	DHSTL12II IO standard is translated to Altera "DIFFERENTIAL 1.2-V HSTL CLASS II" constraint.
5650	HSTLI_12 IO standard is translated to Altera "1.2-V HSTL CLASS I" constraint.
5651	HSTLII_12 IO standard is translated to Altera "1.2-V HSTL CLASS II" constraint.
5652	Altera Cyclone3 IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5656	Altera Cyclone4E IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5657	Altera Cyclone 4GX IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5659	Altera Stratix IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5661	Altera Stratix 2 IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5665	Altera Stratix GX IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5666	SSTL15I IO standard is translated to Altera "SSTL-15 CLASS I" constraint.
5667	SSTL15II IO standard is translated to Altera "SSTL-15 CLASS II" constraint.
5668	DSSTL15I IO standard is translated to Altera "DIFFERENTIAL 1.5-V SSTL CLASS I" constraint.
5669	DSSTL15II IO standard is translated to Altera "DIFFERENTIAL 1.5-V SSTL CLASS II" constraint.
5671	Altera Stratix 3 IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5672	Altera Stratix 2GX IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5675	Altera Stratix 4 IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5676	Altera Max 5 IO standard export/import has been improved. All io standards supported by this device can be exported from Altium constraint file and imported from Altera pad file.
5711	Altera pin file importer has been improved. 3.3V LVCMOS and LVTTL iostandards are imported correctly.

Hardware Support Packages: Device Support - Altera Max V (New Module)

5606	Altera Max V device support has been added to Altium Designer. Download Altera Max V Integrated Libraries

Hardware Support Packages: Device Support - Altera Stratix IV (New Module)

5098	Altera Stratix 4 device support has been added to Altium Designer. Download Altera Stratix IV Integrated Libraries

Importers and Exporters: Importer - Tango-PCB ASCII file

5329	TANGO ASCII file format importer will now work as expected.

Output Generators: Output - ERC

5724	ERC Report output job option default for Report Suppressed Errors changed to False to be consistent with default project option

Output Generators: Output - Gerber

5539	Non pad primitives have been given the applity to generate mask layer expansions when they are on the top or bottom layers. This will simplify the creation of complex pad shapes. More information. View BugCrunch report #67.
5754	Gerber Output for flipped embedded board arrays that have components with rotated offset pads has been corrected.
5805	"Drill symbol limit exceeded" modal dialog is now supressed and warning logged to messages panel instead. View BugCrunch report #652.

Output Generators: Output - ODB

5539	Non pad primitives have been given the applity to generate mask layer expansions when they are on the top or bottom layers. This will simplify the creation of complex pad shapes. More information. View BugCrunch report #67.

Output Generators: Printer - PCB

4452	Footprints can now be printed from a PCB library. View BugCrunch report #109.
5539	Non pad primitives have been given the applity to generate mask layer expansions when they are on the top or bottom layers. This will simplify the creation of complex pad shapes. More information. View BugCrunch report #67.
5805	"Drill symbol limit exceeded" modal dialog is now supressed and warning logged to messages panel instead. View BugCrunch report #652.

Development updating various modules

The development made for the following tickets required changes to our Run Time Libraries, and as a result require majority of the modules to be updated.

4303	Embedded Threads debugging panel is working again (was always empty in R10).
5098	Altera Stratix 4 device support has been added to Altium Designer.
5309	An Access Violation with message "List index out of bounds (-1)" will no longer occur when using any of the grid (tree list view) controls when the memory used by AD is close or over *2GB*.
5586	Access violation on close when a LibPkg is added as a pcb project source document has been fixed
5606	Altera Max 5 device support has been added to Altium Designer.
5689	Altera pin file importer has been improved. Pin file parser correctly imports pin information from Altera pin description tables.
5781	Changed warning displayed during connection to Vault dialog to be based on license subscription instead of AltiumLive plan
5785	The preferences dialog has been improved so that all controls are accessible on lower resolution wide screens, which typically have lower vertical resolutions. View BugCrunch report #482.