Release notes for Altium Designer 10 update (10.545.22410)
Additional Resources
Updated plug-ins from release 10.537.22385 to 10.545.22410
Date: 19 May 2011
System Components: Altium Designer Base
4616 | Now UNC paths will be able to be used when generating ODB++ outputs. |
4905 | An Access Violation with message "Access Violation ''View-1687783792'' is not a valid component name at **address*" when trying to select components from the Navigator Panel for very large design will no longer occur. |
System Components: PCB System
4494 | Flipping a component during move no longer loses the ref point. View BugCrunch report. |
4597 | The actual height of a component that has a 3D body with a non-zero OffsetHeight is now calculated correctly for DRC. View BugCrunch report. |
4717 | Changing Mechanical Layer Pairs assignments (add, remove, update Mechanical Layer Pairs) will now mark the PCB Document as Modified. |
4738 | The "PCB Hole Size Editor" no longer creates multiple entries for the same hole size when old slot hole length is retained after changing the hole type to Round. |
4905 | An Access Violation with message "Access Violation ''View-1687783792'' is not a valid component name at **address*" when trying to select components from the Navigator Panel for very large design will no longer occur. |
System Components: PCB Support
2813 | IBIS converter tool now supports Model Selector keyword and allows selection of the model within the signal integrity model dialog. View BugCrunch report. |
3252 | An issue preventing reflection results from being generated for some designs due to generation of a long combined net name has been fixed. |
4401 | A problem with the list of sch pin in the SI Part Array dialog has been fixed |
4465 | CAMtastic® Gerber Export will no longer create Gerber files that can't be loaded back into CAMtastic® correctly when using RS274X format & Incremental coordinate data. |
4497 | CAMtastic® ODB++ import for embedded board arrays will no longer reset the drill layer pairs for some of the child boards if any of the arrays is mirrored. |
4577 | Allegro Gerber files containing nested polygons will now load correctly in CAMtastic®. |
4581 | CAMtastic® "One or More Layer Types are duplicated/not defined!" information dialogue will no longer be stuck in an infinite loop if the user clicks the "No" button. |
4619 | CAMtastic® Gerber loader will no longer discard OrCAD Gerber files that use M2* command instead of M02* for marking the end of the file. |
System Components: Schematic System
4481 | After pasting a component to the Sch Library panel, the component will now be selected and focused. View BugCrunch report. |
4587 | Shift click now enters inplace edit of selected text object when Shift Click to Select preference is enabled. View BugCrunch report. |
4905 | An Access Violation with message "Access Violation ''View-1687783792'' is not a valid component name at **address*" when trying to select components from the Navigator Panel for very large design will no longer occur. |
System Components: Soft Design System
1377 | The Messages panel now opens on HDL simulation error. |
1479 | Cross probing in the Messages panel is now supported when running HDL simulation with the Aldec OEM simulator. |
3063 | Actel Libero/Designer 9.1 is now supported. |
4922 | Timing constraints are now properly passed to Actel Designer while using Synplify or Synplify For Actel. |
4923 | Rebuilding a project in the Devices View is now waiting for Synplify For Actel to be closed in order to avoid missing or corrupted files to be processed by Actel Designer. |
4928 | The FPGA_DELAY_MAX, FPGA_DELAY_MAX_FROM and FPGA_DELAY_MAX_TO constraints are no longer set with incorrect values for bus signals. |
System Components: Soft Design Support
3501 | Some components from the FPGA Configurable Generic and the FPGA Instruments libraries (including FIFO and LAX) are no longer failing while using Synplify or Synplify for Actel. |
System Components: Soft Design Synthesis Libraries
4632 | Some components from the FPGA Generic library are no longer causing the FPGA flow to fail because they have the same name as an Actel Macro while targeting Actel IGLOO devices. |
Hardware Support Packages: Device Support - Actel IGLOO nano
3315 | FPGA flow is no longer failing because of missing pre-synthesized modules for components from the FPGA Generic library while targeting an Actel IGLOO nano device. |
Output Generators: Output - ODB
4835 | ODB++ Output will now export Signal Layer Polygon Regions to corresponding ODB++ nets in case they are part of any PCB nets. View BugCrunch report. |