Verilog Include Paths and Defines

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Modified by Admin on Sep 13, 2017

Altium Designer 14.3 sees enhanced support for Verilog, with improvements to the way in which include paths are defined at the project-level. In addition, the ability to specify global macro definitions (Defines) is also facilitated through project options. Controls are available in the Verilog Include Paths and Defines region, on the Options tab of the Project Options dialog (Project » Project Options).

Specify Include Paths and Defines for use with your Verilog-based FPGA designs.

As many Include Paths as needed can be specified, and paths can be absolute or relative (relative to the FPGA project file). Force newly added paths to be relative in nature by enabling the Auto-convert To Relative option, prior to adding those paths. Use the arrow controls to the right of the paths listing, to move a selected path up or down in the list accordingly. The software looks for the include file in accordance with this ordering, and uses the first detected match.

Example use of Include files in a Verilog source file. The files are found along the path specified in the project's options (previous image).