High Speed PCB Design

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What is High-Speed PCB Design?

The routing on the printed circuit board joins the component pins to create the connectivity in the design. In a design with slow signal-switching speeds the interconnections can be considered ideal, meaning the signals arrive at their target input pins with the correct signal shape and timing - the routing does not impact on the circuit behavior or performance. For this type of design the PCB designer's job is to create the connectivity in the routing, with their prime electrical considerations being to ensure that the routing is suitable for the current and voltage requirements needed in the circuit.

However, as the signal switching speeds increase this assumption that the routing is ideal, no longer holds. So just when is it time to let go of the assumption that the routing interconnects are ideal, and start treating the routing as part of the circuit? A common rule of thumb that is used is the 1/3 rise time rule. This rule states that if the trace is more than 1/3 of a rise time long, then reflections (ringing) can occur. For example, if the source pin has a 1 nSec rise time, then a route longer than .33 nSec - which is approximately 2 inches in FR4 - must be considered to be a transmission line, making it a candidate for signal integrity issues. If your devices have switching speeds that deliver this sort of rise time and you know you will have routing of this sort of length, then you might well end up with signal integrity issues on the PCB. This design must now be considered a high-speed PCB design and suitable high-speed design principals applied. Remember though, it's the device switching speed, not the clock speed on the board, that determines if it is a high-speed PCB design.

The speed at which the electrical energy can travel along the route is known as the propagation velocity, where:
VP = speed of light / √dielectric constant

Time = 1/3 * rise time
εR = 4 (approximation for FR4)
C = 11.811 in/nSec (speed of light, in inches per nanosecond)

To find the length of route above which the integrity of the signal could become a problem:
LR = Time * VP
LR = Time * C / √ εR
LR = .33 * 11.811 / 2
LR = 1.95 in

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