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Altium provides an extensive range of components to accompany Altium products. Current and new components are delivered via the Altium Content Vault, along with reference designs and templates. The components can be accessed via a browser, or they can be accessed from the Vaults panel in Altium Designer.

Altium Legacy Libraries

Altium Designer 10 Libraries

Additional, independently developed, libraries and ancillary support files.

Third-Party Libraries

Vendor Codes used in Manufacturer libraries.

Vendor Codes

Naming Conventions

PCB footprints - surface mount

PCB footprints for surface mount packages are built to the standards developed by IPC - "Association Connecting Electronics Industries". IPC claims that these land patterns are transparent to the manufacturing process but recommends that they should be optimized to suit the soldering type (wave, reflow) and assembly (components mounted on one or both sides of the board, etc).

Land patterns for surface mount components follow the assumptions and equations found in standards IPC-SM-782A, Amendment 1 (October 1996) and Amendment 2 (April 1999) and IPC-7351 (February 2005). The pad diameters for the BGA and CGA packages are defined by the etched copper, rather than by the solder mask.

Under the IPC-7351 standard, three different footprints levels are specified:

Low-Density applications with a ‘maximum’ footprint size, designated by the letter ‘M’

Medium-Density applications with a ‘moderate’ footprint size, designated by the letter ‘N’

High-Density applications with a ‘minimum’ footprint size, designated by the letter ‘L’

These designation letters are appended to Altium library and footprint names to identify the density level. Only ‘nominal’ level footprints are drawn for BGA and CGA packages. IPC-7351 compliant footprints are found in Altium Designer 6.3 version libraries and later versions. The IPC-7351 standard: ”Generic Requirements for Surface Mount Design and Land Pattern Standard” supersedes IPC-SM-782A (Amendments 1 & 2).


All PCB footprint dimensions are given in metric units. Hard metric dimensions are employed in accordance with the JEDEC JC-11 "Metrication Policy", SPP-003B (February 1998). Departures to this policy are made for some silkscreen dimensions and critical dimensions such as pitch and row spacing.

Footprint acronyms

A unique name is assigned to each footprint. The naming convention is in sympathy with the IPC component names and the JEDEC Standard, JESD30-B, "Descriptive Designation System for Semiconductor-Device Packages" (April 1995).

The IPC-7351 (September 2005) and IPC-7351A (July 2006) “Naming Convention for Standard SMT Land Patterns” are applied to the IPC-7350 series components.

Schematic Naming

Pin Names

As a general rule pins are assigned the same name as provided in the manufacturers datasheet. For some smaller components it is prudent to use an abbreviation if the pin name is lengthy, in order to provide a clean-looking symbol, eg. AUX for Auxiliary. However different manufacturers regularly use different abbreviations for the same name or use the same abbreviation for different names. On occasions, these inconsistencies appear within the datasheets of the same manufacturer. For example, GND and GRD for Ground. In order to provide a consistency to schematic symbols, a table of abbreviations for over 600 names has been compiled using popular abbreviations employed by a number of manufacturers and appendix A of the "IEEE Standard for Logic Circuit Diagrams" ANSI/IEEE Std 991 - 1986.

Class designation letter

Default designators are assigned in accordance with Section 22 of IEEE Std 315-1975 (Reaff 1993) "Graphic Symbols for Electrical and Electronic Diagrams".

Graphic symbols - normal mode

Logic diagrams for gates and buffers/drivers are drawn using the time-honored, distinctive-shape logic symbols as prescribed in appendix A of IEEE Std 91.

Simple devices, such as transistors and amplifiers, are drawn according to IEEE Std 315-1975 (Reaff 1993), "Standard Graphic Symbols for Electrical and Electronics Diagrams" and its supplement, IEEE Std 315A-1986.

The pin configuration for remaining components follows the layout presented in the application schematics or the function block diagram of the component. Additional in-house conventions have been refined to standardize the presentation of common components.


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