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The SPICE Options page of the Analyses Setup dialog enables you to define advanced simulation options, including the values of SPICE variables, the integration method used by the Simulation Engine and the simulation reference net.

You can define the numerical integration method used for simulations in the Integration method field. The Trapezoidal method is relatively fast and accurate, but tends to oscillate under certain conditions. The Gear methods require longer simulation times, but tend to be more stable. Using a higher gear order theoretically leads to more accurate results, but increases simulation time. The default method is Trapezoidal.

All of the digital components supplied in the component libraries have hidden power pins (VCC and GND for the TTL devices, and VDD and GND for the CMOS series devices). These hidden power pins are automatically connected during netlisting and assigned the voltages specified in the Digital Supply VCC and Digital Supply VDD fields. To change the default power supply values, enter new values in these fields. The defaults are VCC = 5, VDD = 15.

To power any digital components in your circuit from nets other than VCC (or VDD for CMOS) you must include source components to create the appropriate voltages, un-hide the power pins for each component and wire the power pins to the appropriate power nets.

When a simulation is run, all data that is collected for all available signals is referenced to a specific net in the circuit. This net is defined in the Spice Reference Net Name field and, by default, is the GND net. To run a transient simulation which references a net other than ground, enter the net name in this field.

The main area of this page of the dialog lists options that give you direct access to SPICE variables, from where you can change iteration limits, error tolerances, etc.

To change the value of a SPICE variable, click inside the associated Value column entry, edit the value as required, then press Enter or click outside of the column entry, to change the variable to the new value.

To return an option to its default value, simply enable the associated entry in the Def column.

The following details each of the SPICE variables contained in the list:

SPICE Option

Description

Default Value

ABSTOL

Sets the absolute current error tolerance (in Amps).

1.000p

ACCT

Causes accounting and run-time statistics to be displayed.

Disabled

ADCSTEP

Minimum step size required to register an event on the input of the internal A/D converters.

10.00m

AUTOPARTIAL

Enables automatic computation of partial derivatives for XSpice code modules.

Disabled

BADMOS3

Uses the older version of the MOS3 model with the "kappa" discontinuity.

Disabled

BOOLH

Sets the high output level of a Boolean expression.

4.500

BOOLL

Sets the low output level of a Boolean expression.

0.000

BOOLT

Sets the input threshold level of a Boolean expression.

1.500

BYPASS

Enables device bypass scheme for nonlinear model evaluation.

Enabled

CHGTOL

Provides lower limit on capacitor charge or inductor flux (in Coulombs); used in the LTE timestep control algorithm.

10.00e-15

CONVABSSTEP

Sets limit of the absolute step size in solving for the DC operating point convergence for code model inputs.

100.0m

CONVLIMIT

Disables convergence algorithm used in some built-in component models.

Disabled

CONVSTEP

Sets the limit of the relative step size in solving for the DC operating point convergence for code model inputs.

250.0m

CURRENTMNS

Sets scale factor used to determine min supply current when value not specified in SimCode model.

1.500

CURRENTMXS

Scale factor used to determine max supply current when value not specified in SimCode model.

500.0m

DEFAD

Sets the MOS drain diffusion area.

0.000

DEFAS

Sets the MOS source diffusion area.

0.000

DEFL

Sets the MOS channel length (in micrometers).

100.0

DEFW

Sets the MOS channel width (in micrometers).

100.0

DRIVEMNS

Sets scale factor used to determine min output drive capacity when value not specified in SimCode model.

1.500

DRIVEMXS

Sets scale factor used to determine max output drive capacity when value is not specified in SimCode model.

500.0m

DRVMNTYMX

Temporary global override for output drive capacity index on SimCode devices (None, Minimum, Typical, Maximum).

None

GMIN

Sets min conductance (max resistance) of any device in the circuit (in mhos). Also sets value of the conductance that is placed in parallel with each pn junction in the circuit.

1.000p

GMINSTEP

Sets the number of steps in the GMIN stepping algorithm. When set to 0, GMIN stepping is disabled, making source stepping the simulator's default DC (operating point) convergence algorithm.

10

IMNTYMX

Temporary global override for supply current index on SimCode devices (None, Minimum, Typical, Maximum).

None

ITL1

Sets Operating Point Analysis iteration limit.

100

ITL2

Sets DC Analysis iteration limit.

50

ITL3

Sets lower Transient Analysis iteration limit.

4

ITL4

Sets Transient Analysis timepoint iteration limit.

40

ITL5

Sets Transient Analysis total iteration limit.

5000

KEEPOPINFO

Retains operating point information when an AC Analysis is run.

Disabled

LDMNTYMX

Temporary global override for input loading index on SimCode devices (None, Minimum, Typical, Maximum).

None

LIST

Displays a comprehensive list of all elements in the circuit with connectivity and values.

Disabled

LOADMNS

Sets scale factor used to determine min input loading (max input resistance) when value not specified in SimCode model.

1.500

LOADMXS

Sets scale factor used to determine max input loading (min input resistance) when value not specified in SimCode model.

500.0m

MAXEVTITER

Sets the max number of event iterations for DC (operating point) convergence.

0

MAXOPALTER

Sets the max number of analog/event alternations for DC (operating point) convergence.

0

MINBREAK

Sets the min time between breakpoints (in seconds).

0 (Automatic)

NOOPALTER

Enables DC (operating point) alternations.

Disabled

NOOPITER

Skip directly to GMIN stepping algorithm.

Disabled

OPTS

Displays a list of all standard SPICE3 Option parameter settings.

Disabled

PIVREL

Sets relative ratio between the largest column entry in the matrix and an acceptable pivot value. The value must be between 0 and 1.

1.000m

PIVTOL

Sets the absolute min value for a matrix entry to be accepted as a pivot.

100.0e-15

PROPMNS

Sets scale factor used to determine min propagation delay when value is not specified in SimCode model.

500.0m

PROPMXS

Sets scale factor used to determine max propagation delay when value is not specified in SimCode model.

1.500

RAMPTIME

Controls turn-on time of independent sources and capacitor and inductor initial conditions from zero to their final value during the time period specified (in seconds).

0.000

RELTOL

Sets relative error tolerance of the program. The value must be between 0 and 1.

1.000m

RSHUNT

Value (in ohms) of resistors added between each circuit node and ground, helping to eliminate problems such as "singular matrix" errors. In general, the value of RSHUNT should be set to a very high resistance (1e+12).

0.000 (No shunt resistors)

SIMWARN

Allows SimCode warning messages to be displayed at run time. SimCode warnings may include information concerning timing violations (tsetup, thold, etc.) or indicate supply voltage dropping below device specifications (None, No, Yes).

None

SRCSTEP

Sets the number of steps in the source stepping algorithm for DC (operating point) convergence.

10

TEMP

Sets the actual operating temperature of the circuit (in Degrees C). Any deviation from TNOM will produce a change in the simulation results. Where a device model has a Temperature parameter that can be set at the component-level, setting a value for that parameter will override TEMP.

27.00

TNOM

Sets the nominal temperature for which device models are created (in Degrees C). Where a device model has a TNOM parameter that can be set at the model file-level, setting a value for that parameter will override TNOM.

27.00

TPMNTYMX

Temporary global override for propagation delay index on SimCode devices (None, Minimum, Typical, Maximum).

None

TRTOL

Used in the LTE timestep control algorithm. This is an estimate of the factor by which SPICE overestimates the actual truncation error.

7.000

TRYTOCOMPACT

Applicable to the LTRA model. When specified, the simulator tries to condense LTRA transmission line's past history of input voltages and currents

Disabled

VNTOL

Sets the absolute voltage tolerance of the program (in Volts).

1.000u

Notes

In general, you should not have to change any of the advanced SPICE parameters in this page of the dialog for accurate simulation. Only change these options if you have a good understanding of SPICE simulation parameters.
When troubleshooting Transient analysis failure, try setting:

  • ABSTOL=RELTOL * (lowest current magnitude in the circuit)
  • VNTOL= RELTOL *  (lowest voltage magnitude in the circuit)

Raising the value of GMIN may help with convergence, but decreases accuracy.

ITL1 may need to be raised as high as 500 for many circuits.

ITL2 may need to be raised as high as 200 for some circuits.

ITL3 is not implemented in SPICE3. It is provided for compatibility in creating SPICE2 netlists.

Raising ITL4 to 100 or more may help to eliminate "timestep too small" errors improving both convergence and speed.

ITL5 is not implemented in SPICE3. It is provided for compatibility in creating SPICE2 netlists.

Enabling the KEEPOPINFO option is useful if the circuit is large and you do not want to run a redundant Operating Point Analysis.

In the numerical pivoting algorithm, the allowed min pivot is determined by:

EPSREL=AMAX1(PIVREL * MAXVAL, PIVTOL)

where MAXVAL is the max element in the column where a pivot is sought (partial pivoting).

With respect to the RELTOL option, larger values mean faster simulation time, but less accuracy.

 

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