PB02 Resources - CF Card Reader

The PB02 provides a reader for Type 1 Compact Flash (CF) memory cards. The Compact Flash interface is smaller than, but electrically identical to, the PCMCIA-ATA interface.

Figure 1. Compact Flash (CF) memory card reader.

The -ATA SEL input (pin 9) has been tied to GND, placing the interface in TrueIDE mode. In this mode, the CF Interface includes all of the signals found in the standard ATA/IDE interface.

Power for the CF card reader is sourced from the output of an adjustable linear voltage regulator – a TPS75501 device, from Texas Instruments.

Figure 2. TPS75501 adjustable
linear voltage regulator.

The regulator is enabled/disabled under the control of signal CF_CARD_POWER, which is sourced from an IDE Controller within the FPGA design. The Controller takes this signal Low to enable the regulator and power the CF card reader for normal operation.
 

 
The actual voltage level supplied to the CF card reader is determined by three resistors connected on the output side of the regulator – R1_PS, R2_PS and R3_PS – and calculated using the following expression:

Vout = 1.224V * (1 + ((R2_PS + R3_PS) / R1_PS)

The following resistor values are used:

• R1_PS: 15K

• R2_PS: 3K3

• R3_PS: 22K.

Feeding these values back into the expression gives an output voltage supplied to pins 13 and 38 of the reader of 3.288V. While the regulator is enabled and the 3.3V supply available to the CF card reader, an associated LED (labeled '3V3CF ON' and designated LED2) will be lit (Green).

The CF card reader also provides dual card detection signals (CF_CARD_DET0, CF_CARD_DET1), to flag whether a card has been inserted. When a CF card is not inserted, these signals deliver High to the FPGA design, courtesy of two 4K7 pullup resistors to the PB02's 3.3V supply. When a card is fully inserted into the header, these two signals become grounded (connected to ground on the CF card itself) and the FPGA design therefore receives Low on these two lines.

An additional signal from the FPGA design – LED_ACTIVE – can be used to indicate when the host processor in the design is accessing the CF card. Taking this line High will result in the LED at the top-right of the board (labeled 'HDD ACTIVE' and designated LED1) becoming lit (Red).

Although the LED_ACTIVE signal is essentially standalone, and can be controlled by any circuitry in the design, you might typically connect to it from the CF_IDE_ACTIVITY output of an IDE Controller in the design. This line is actually an inverted copy of the active-Low CF_IDE_DASP input line to the Controller.
 

Location on Board

The CF card reader (designated J2) is located on the component side of the board, directly beneath the 3.5" ATA/IDE header.

The TPS75501 (designated U11) is located on the solder side, to the right of the SD card reader.

The 'HDD ACTIVE' (LED1) and '3V3CF ON' (LED2) LEDs are located on the component side, toward the top-right corner of the board.

Figure 3. HDD activity LED
(LED1) and CF 3.3V power
ON LED (LED2).

Schematic Reference

The CF card reader circuitry can be found on the following sheets of the peripheral board schematics:

• IDE_CF.SchDoc (entitled IDE Connector)

• IDE_TERMINATOR.SchDoc (entitled IDE Terminator).

Design Interface Component

Table 1 summarizes the available design interface component that can be placed from the FPGA PB02 Port-Plugin.IntLib for access to, and communications with, a Compact Flash memory card.

Should you wish to use the 'HDD ACTIVE' LED, you will need to place the relevant design interface component, as summarized in Table 2.

Further Device Information

For more information on the TPS75501 device, refer to the datasheet (tps75501.pdf) available at www.ti.com.