PB02 Resources - ATA and IDE Interfaces

The ATA (Advanced Technology Attachment) bus interface – commonly referred to as the IDE (Integrated Drive Electronics) bus interface – is a standard interface used for connection of storage devices, such as hard disk drives, to a processor in a computer.

The PB02 provides three standard parallel ATA/IDE interfaces, providing for connection of an IDE-compatible storage-based device, such as a hard disk, CD-ROM drive or DVD-ROM drive, directly to the Desktop NanoBoard NB2DSK01. Three popular form-formats are catered for:

• 1.8" ATA/IDE interface – courtesy of a 2x20 FFC header. Connection is made using a 40-way flat-flex cable. This connector would typically be used to interface to a micro 'media' hard drive, as used for example in MP3 music/media players.
   
  
  Figure 1. 2x20 FFC header providing the 1.8" ATA/IDE
  interface.
   
• 2.5" ATA/IDE interface – courtesy of a 2x22 boxed header. Connection is made using a 44-pin flat cable. This connector would typically be used to interface to a Laptop IDE-compatible storage device.
   
  
  Figure 2. 2x22 boxed header providing the 2.5" ATA/IDE interface.
   
• 3.5" ATA/IDE interface – courtesy of a 2x20 IDC header. Connection is made using a 40/80-way ribbon cable. This connector would typically be used to interface to a Desktop IDE-compatible storage device.
   
  
  Figure 3. 2x20 IDC header providing the 3.5" ATA/IDE interface.

 
Interface control to a storage device attached to one of the three ATA/IDE interfaces is performed using an IDE Controller, which is placed in the FPGA design and sits between a processor in the design and the IDE resource on the PB02.

An additional signal from the FPGA design – LED_ACTIVE – can be used to indicate when the host processor in the design is accessing the attached storage device. Taking this line High will result in the LED at the top-right of the board (labeled 'HDD ACTIVE' and designated LED1) becoming lit (Red).

Although the LED_ACTIVE signal is essentially standalone, and can be controlled by any circuitry in the design, you might typically connect to it from the CF_IDE_ACTIVITY output of an IDE Controller in the design. This line is actually an inverted copy of the active-Low CF_IDE_DASP input line to the Controller.
 

Location on Board

The three ATA/IDE headers, labeled '1.8" ATA' (designated J4), '2.5"ATA' (designated J3) and '3.5" ATA' (designated J1), are located on the component side of the board and appear from the top of the board in that order.

The 'HDD ACTIVE' (LED1) LED is located on the component side, toward the top-right corner of the board.

Figure 4. HDD activity
LED (LED1).

Schematic Reference

ATA/IDE interface circuitry can be found on the following sheets of the peripheral board schematics:

• IDE_CF.SchDoc (entitled IDE Connector)

• IDE_Terminator.SchDoc (entitled IDE Terminator)

Design Interface Component

Table 1 summarizes the available design interface component that can be placed from the FPGA PB02 Port-Plugin.IntLib for access to, and communications through, an ATA/IDE interface.

Should you wish to use the 'HDD ACTIVE' LED, you will need to place the relevant design interface component, as summarized in Table 2.