NanoBoard 3000 - User USB Port

The NanoBoard 3000 provides a USB 2.0 port for use by a design programmed into the board's User FPGA. The port is provided courtesy of a USB B-type connector.

USB 2.0 interface port accessible
from an FPGA design.

Providing the high-speed interface between a processor in an FPGA design and the USB bus is an EZ-USB SX2™ device (CY7C68001-56LFC, from Cypress Semiconductor). This device has a built-in USB transceiver and a Serial Interface Engine (SIE), which automatically manages the USB protocol. The device is powered by the motherboard's 3.3V supply and is configured to provide a 16-bit bidirectional data bus to/from the processor.

The USB interface device supports operation at Full (12Mbps) or High (480Mbps) speed.

Internal clocking for the USB transceiver (and various internal logic) is supplied from an internal PLL, which itself is driven by an external 24MHz crystal connected across the device's XTALIN and XTALOUT pins.

Reset of the USB interface device is provided through use of a supervisory reset circuit device – a MAX6315, from Maxim. This device will assert the reset signal to the CY7C68001 (active Low) if its 3.3V supply voltage dips below 2.63V (nominal), or if it receives an external reset signal from the processor in the FPGA design. The reset signal will remain asserted for a minimum of 1ms (typically 1.5ms) after the supply voltage rises above this threshold, and/or the processor deasserts its reset signal.

The USB data lines (D+, D-) are protected against high transient voltages through the use of a low-capacitance transient voltage suppressor device – a NUP2201MR6, from ON Semiconductor.

Location on Board

The USB connector (designated J9) is located along the bottom edge on the solder side of the board. Looking from the front, it can be found at the far right – positioned below the DIP-Switch.

USB Port (as seen from the front of the board).

The CY7C68001 device (designated U19) and the NUP2201MR6 device (designated U18) are also located on the solder side of the board, directly above the USB port itself. The MAX6315 device (designated U49) is located to the top-left of the CY7C68001 device.

USB high-speed interface device
(U19), voltage suppressor (U18)
and supervisory reset circuit (U49).

The 24MHz crystal (designated Y4) is located on the solder side of the board, to the right of the CY7C68001 device associated with the Host USB interface (U56).

24MHz crystal used to provide the
USB clock.

Schematic Reference

The USB circuitry can be found on the following sheets of the motherboard schematics:

• Sheet 56 (USB_CY7C68001-56LFC.SchDoc, entitled High-Speed USB 2.0 Controller)

• Sheet 57 (OSC_24MHZ.SchDoc, entitled 24MHz Oscillator) – the 24MHz crystal used to provide the USB clock.

• Sheet 58 (CON_MINI_USBB_RA_KME04-USBMU03A01-1.SchDoc, entitled USB 2.0 Type B Connector)

Design Interface Component

Table 1 summarizes the available design interface component that can be placed from the FPGA NB3000 Port-Plugin.IntLib to access the USB interface.

Further Device Information

For more information on the CY7C68001 device, refer to the datasheet (CY7C68001.pdf) available at www.cypress.com.

For more information on the MAX6315 device, refer to the datasheet (MAX6315.pdf) available at www.maxim-ic.com.

For more information on the NUP2201MR6 device, refer to the datasheet (NUP2201MR6-D.pdf) available at www.onsemi.com.