NanoBoard 3000 - User IO Headers
The NanoBoard 3000 includes two I/O headers that allow user-defined hardware to be interfaced to the User FPGA. These 20-pin headers – designated UH1
and UH2
– cater for a total of 36 User FPGA I/O signals, 18 wired to each.
Each header also supplies power (pin 1) and ground (pin 20) signals. The power supply level is user-selectable via an associated configurable jumper header – designated JP1
and JP2
respectively. Table 1 summarizes the effect of jumper placement on these headers.
Jumper Position | Description |
---|---|
1-2 | Put a jumper on these pins to provide the motherboard's 5V supply. |
3-4 | Put a jumper on these pins to provide the motherboard's 3.3V supply. |
The 36 I/O signals are also made available to the motherboard's prototyping area.
Location on Board
The two headers, labeled 'User Header A'
(designated UH1
) and 'User Header B'
(designated UH2
) respectively, are located on the component side of the board, above the prototyping area.
The two configurable jumper headers (JP1
and JP2
) are also located on the component side, directly to the left of their respective user headers (UH1
and UH2
).
Schematic Reference
The User I/O headers can be found on Sheet 50 (CON_USER_20WBOXHDRRAMx2.SchDoc
, entitled 36-Way User I/O Headers) of the motherboard schematics.
Design Interface Component
Table 2 summarizes the available design interface components that can be placed from the FPGA NB3000 Port-Plugin.IntLib
, to access and use the two I/O headers.
Component Symbol | Component Name | Description |
---|---|---|
| USER_HEADER_A | Place this component to access and use |
| USER_HEADER_B | Place this component to access and use |