WB_UART8_V2 - Wishbone Serial Communications Port (AD10)

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Parent article: FPGA Peripheral Components - Wishbone

The WB_UART8_V2 peripheral has been enhanced in Altium Designer 10. It now provides the following new features over its predecessor:

  • Word length can be set to 5, 6, 7, or 8 bits
  • Parity can be set to None, Odd, Even, or User-Defined
  • 1 or 2 stop bits
  • Additional Serial Communication Parameters register (PARM)
  • Additional Version information register (VERSION)

On the hardware side (the peripheral core itself) changes affect, and are confined to, the internal register set. On the Software Platform side, supporting drivers have been enhanced and slightly changed to accommodate the new core. This article outlines the changes only, and should be read in conjunction with the existing documentation for the peripheral, the link to which can be found in the See Also section of this page.

Although the register set for this version of the core has changed (and expanded!), it is fully backwards-compatible with the existing WB_UART8_V2.

Register Interface Changes

The following table summarizes the register set for the new WB_UART8_V2 peripheral, with specific changes to existing registers, and newly added registers, detailed in sections thereafter.

Address

Register

Contents

0000

BRGHIGH

High byte of baudrate generator

0001

BRGMID

Middle byte of baudrate generator

0010

BRGLOW

Low byte of baudrate generator

0011

LCR

Line control

0100

STATUS

UART status register

0101

INTMASK_SET

Interrupt mask read & set

0110

INTMASK_RST

Interrupt mask reset

0111

SBUF

Serial transmit & receive buffer

1000

TXLOWMARK

Transmitter low watermark

1001

RXHIGHMARK

Receiver high watermark

1010

RXLOWMARK

Receiver low watermark

1011

RXDTO

Receiver timeout

1100

ICD

Inter-character delay

1101

BRKLEN

Break length

1110

PARM

Serial communication parameters

1111

VERSION

Core version

Baudrate Generator (BRGHIGH, BRGMID, BRGLOW)

The baudrate generator consists of a counter that is increased with the value set in registers 0, 1 and 2 on each rising edge of the CLK_I signal. When it overflows, it generates a state change in the UART state machine. The internal state machine consists of 8 cycles per bit.

Line Control Register (LCR)

The Line Control register consists of the following bits:

Bit

Signal

Content

0

CTSEN

Use CTS/RTS handshake if set

1

FORCERTS

Forces RTS to a known state

2

RTSVAL

Value of RTS if FORCERTS is set

3

FRAMERR

A framing error was detected by the receiver

4

PARERR

A parity error was detected by the receiver, or value of parity bit when user-defined parity is selected

5

RXD

Raw value of RXD input

6

BREAK

A BREAK condition was detected by the receiver

7

CTS

Raw value of CTS input

The FRAMERR and PARERR bits are new in version 3 of the core. They will read as '0' in older versions.

FRAMERR will be '1' in case of a BREAK (since the receiver detected a stop bit to be '0'!). Likewise, PARERR may be set in case of a BREAK. You should first detect for BREAK, if that's not set, check for FRAMERR and finally for PARERR (provided FRAMERR is not set either).

The error and break bits indicate the status of the top reception of the FIFO. Clear them by reading the receiver FIFO once.

Status and Interrupt Control Registers (STATUS, INTMASK_SET, INTMASK_RST)

The Status and Interrupt Control registers consist of the following bits:

Bit

Signal

Content

0

TXFULL

Transmitter FIFO is full

1

TXEMPTY

Transmitter FIFO is empty

2

TXLOW

Transmitter FIFO is almost empty

3

TXSHEMPTY

Transmitter shift register is empty

4

RXTIMEOUT

Receive FIFO has unread chars and timed out

5

RXNEMPTY

Receive FIFO is not empty

6

RXHIGH

Receive FIFO is almost full

7

RXFULL

Receive FIFO is overrun

Serial Communication Parameters Register (PARM)

The Serial Communication Parameters register consists of the following bits:

Bit

Signal

Content

0..1

WORDLEN

Word length
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits

2

STOPBITS

Defines the number of stopbits:
0 = 1 stopbit
1 = 2 stopbits

3-4

PARITY

Parity
00 = None
01 = Even
10 = User
11 = Odd

5

PARITYVAL

Value of parity bit if PARITY is set to "User"

This register is new in this version of the core. Writing to it in older versions does not have any effect, reading will return an unknown value.

Core Version Register (VERSION)

Read this register twice – without reading any other register in-between – to get the version information. If the MSB changes state (either from '1' to '0' or vice-versa), the other 7 bits contain a version number. If the MSB does not change, the core version is invalid. In this case, assume a core older than version 3.

Software Platform Changes

To accommodate this new version of the WB_UART8_V2, the relevant Software Platform drivers have been enhanced and modified. In most cases, using the new drivers will not require any change in your application.

Modified Function - uart8_getchar()

The following special values can now be inclusively OR'ed in the value returned from uart8_getchar():

  • UART8_PARERR
  • UART8_FRAMERR

These values indicate communication errors when receiving data. PARERR indicates a parity error, FRAMERR indicates a framing error. Note: When user parity is selected, UART8_PARERR is used to indicate the user parity, this is not necessarily an error!

New Function - uart8_get_version()

Parameters: drv – a pointer to the driver structure as returned by uart8_open()

Returns: core version number

Use the function uart8_get_version (after you have opened the driver using uart8_open()) to retrieve the core version. The function will return 3 or higher for a core version 3 or later, it will return version 2 otherwise.

New Function - uart8_set_parameters()

Parameters: drv – a pointer to the driver structure as returned by uart8_open()
                         baudrate – requested communication speed in bits per second
                         parity – parity to be set
                         wordlen – word length (5, 6 7 or 8 bits)
                         stopbits – number of stop bits (should be 1 or 2)

Returns: nothing

Use this function to set the communication parameters. The core is initialized after reset to no parity, 8 data bits, 1 stop bit and no speed (thus it's effectively disabled). This behavior is the same as previous WB_UART8 cores.

The parity parameter can be:

  • UART8_NO_PARITY – no parity
  • UART8_ODD_PARITY – odd parity
  • UART8_EVEN_PARITY – even parity
  • UART8_USER_PARITY – user parity

When user parity is set, use the function uart8_set_user_parity() to define its value.

New Function - uart8_set_user_parity()

Parameters: drv – a pointer to the driver structure as returned by uart8_open()
                         val – the value of the parity bit to be used for transmission

Returns: nothing

Use this function to define the value of the parity bit for transmission, when the parity is set to "user parity". This parity bit does not depend on the contents of the data transmitted, but will be set according to the value defined in this function.

Note: When receiving data in user parity, the UART8_PARERR indicates the remote device sent a '1' in the parity slot, otherwise it sent a '0'.

New Function - uart8_ignore()

Parameters: drv – a pointer to the driver structure as returned by uart8_open()
                         rx_mask – a mask indicating what conditions should not be reported by getchar()

Returns: nothing

By default, breaks as well as parity and framing errors are reported to the user when using getchar(). Use this function to tell the driver it should ignore (some of) these conditions and simply skip errors and/or breaks when receiving data. The mask should consist of a logical OR of UART8_BREAK, UART8_PARERR and UART8_FRAMERR values. Thus, if you want to ignore framing and parity errors but do want to know about breaks, call uart8_ignore with mask value set to UART8_PARERR|UART8_FRAMERR.

uart8_read() never reports break and/or error conditions but always skips them!

Other Behavioral Changes

In previous versions of the driver the receiver, when in interrupt mode, stalled if it detected a break condition whilst there was another break already waiting. This no longer happens – breaks are now handled similar to any other character.

Example Reference Design

An example design, demonstrating the use of the enhanced UART peripheral, is included as part of your Altium Designer installation:

  • UART_Error_Handling.PrjFpg – located in the \Examples\Soft Designs\Communication\UART ComError Handling folder.

See Also

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