WB_MEM_CTRL Configuration - Parallel Flash Settings
When the chosen memory type is Parallel FLASH, the Configure (Memory Controller) dialog will appear as shown in Figure 1.
The following sections detail each of the configuration options available.
Size of Parallel Flash Array
Use this region to specify the size of the physical memory that you are interfacing to. The width of the Flash memory interface address bus(es) and also the ADR_I input line will update accordingly upon leaving the dialog.
Table 1 lists the supported Flash memory sizes and the corresponding size of the address buses for each configuration of the Memory Controller.
Flash Size | Address Bus Sizing for each Memory Layout | |||||||||
1 x 8-bit | 2 x 8-bit | 1 x 16-bit | 2 x 16-bit | 1 x 32-bit | ||||||
ADR_I | FLASH_A | ADR_I | FLASH_A | ADR_I | FLASH_A | ADR_I | FLASH0_A FLASH1_A | ADR_I | FLASH_A | |
1Kb | 10 | 10 | 10 | 9 | 10 | 9 | 10 | 8 | 10 | 8 |
2Kb | 11 | 11 | 11 | 10 | 11 | 10 | 11 | 9 | 11 | 9 |
4Kb | 12 | 12 | 12 | 11 | 12 | 11 | 12 | 10 | 12 | 10 |
8Kb | 13 | 13 | 13 | 12 | 13 | 12 | 13 | 11 | 13 | 11 |
16Kb | 14 | 14 | 14 | 13 | 14 | 13 | 14 | 12 | 14 | 12 |
32Kb | 15 | 15 | 15 | 14 | 15 | 14 | 15 | 13 | 15 | 13 |
64Kb | 16 | 16 | 16 | 15 | 16 | 15 | 16 | 14 | 16 | 14 |
128Kb | 17 | 17 | 17 | 16 | 17 | 16 | 17 | 15 | 17 | 15 |
256Kb | 18 | 18 | 18 | 17 | 18 | 17 | 18 | 16 | 18 | 16 |
512Kb | 19 | 19 | 19 | 18 | 19 | 18 | 19 | 17 | 19 | 17 |
1Mb | 20 | 20 | 20 | 19 | 20 | 19 | 20 | 18 | 20 | 18 |
2Mb | 21 | 21 | 21 | 20 | 21 | 20 | 21 | 19 | 21 | 19 |
4Mb | 22 | 22 | 22 | 21 | 22 | 21 | 22 | 20 | 22 | 20 |
8Mb | 23 | 23 | 23 | 22 | 23 | 22 | 23 | 21 | 23 | 21 |
16Mb | 24 | 24 | 24 | 23 | 24 | 23 | 24 | 22 | 24 | 22 |
32Mb | 25 | 25 | 25 | 24 | 25 | 24 | 25 | 23 | 25 | 23 |
64Mb | 26 | 26 | 26 | 25 | 26 | 25 | 26 | 24 | 26 | 24 |
128Mb | 27 | 27 | 27 | 26 | 27 | 26 | 27 | 25 | 27 | 25 |
Memory Layout
Use the drop-down available in this region of the dialog to select the layout for the physical memory:
- 1 x 32-bit Wide Device
- 1 x 16-bit Wide Device
- 1 x 8-bit Wide Device
- 2 x 16-bit Wide Devices
- 2 x 8-bit Wide Devices.
The schematic symbol for the placed Memory Controller will automatically be updated to reflect your selection, upon leaving the dialog.
In addition to determining the interface pinout for connection to the physical memory device(s), the memory layout also determines the number of accesses required to read or write a single 32-bit word.
Clock Cycles for Reading and Writing
These two regions of the dialog allow you to specify the number of clock cycles (of CLK_I) required to perform a read or write operation respectively.
Reading
A minimum of two clock cycles are required for a zero wait-state read, which equates to 40ns for a 50MHz system clock (CLK_I). By default, the number of clock cycles required for a read operation is set to 4.
Writing
The following default timing settings are used for the three stages of a write operation:
- 1 clock cycle for address set-up
- 5 clock cycles for write pulse
- 1 clock cycle for post-write address hold.
A minimum of three clock cycles (one per stage) are required for each write operation, which equates to 60ns for a 50MHz system clock (CLK_I).