WB_MEM_CTRL - Interfacing

For 32-bit processors the physical interface to the outside world is always 32 bits wide. Since the addressing has a byte-level resolution, this means that up to four "packets" of data (bytes) can be loaded or stored during a single memory access. To accommodate this requirement all memory accesses (8-bit, 16-bit and 32-bit) are handled in a specific way.

Each 32-bit read and write can be considered as a read or write through four "byte-lanes". These byte-lanes are marked as valid by the corresponding bits in the ME_SEL_O[3..0] signal of the processor's External Memory interface. Each bit will be High if the byte data in that lane is valid. This allows a single byte to be written to 32-bit wide memory without needing to use a slower read-modify-write cycle.

The instructions of the processor require that all 32-bit load/store operations be aligned on 4-byte boundaries and all 16-bit load/store operations be aligned on 2-byte boundaries. Byte operations (8-bit) can be to any address.

To complete a byte load or store, the processor will position the byte data in the correct byte-lane and set the ME_SEL_O signal for that lane High. The appropriately-configured Memory Controller must then only enable writing on the relevant 8-bits of data from the 32-bit word.

When reading, the processor will put the relevant 8- or 16-bit value into the LSB's of the 32-bit word. What happens with the remaining bits depends on the operation:

• for an unsigned read, the processor will pad-out the remaining 24 or 16 bits respectively with zeroes

• for a byte load/store, the processor will sign-extend from bit 8

• for a half-word load/store, the processor will sign-extend from bit 16.

The process described happens transparently because memory devices are always seen by the processor as 32 bits wide. Even when connecting to small 8- or 16-bit physical memories, the interfacing Memory Controller device will, as far as the processor is concerned, make the memory look like it is 32 bits wide.

When connecting to 2 x 8-bit or 2 x 16-bit physical memory, the two distinct physical devices are treated as a single memory space. In such cases, the memory device connected to interface 0 will be treated as the lower byte or halfword and the device connected to interface 1 the upper byte or halfword respectively.

For 16-bit SRAM devices, the SRAM_UB and SRAM_LB signals are used by the Memory Controller to direct the relevant byte of data to/retrieve the relevant byte of data from, the appropriate byte-location at the specified address in memory:

• Byte 0 (i.e. SEL_I (0)) will be directed to/retrieved from the lower byte of the device connected to the SRAM0 interface

• Byte 1 (i.e. SEL_I (1)) will be directed to/retrieved from the upper byte of the device connected to the SRAM0 interface

• Byte 2 (i.e. SEL_I (2)) will be directed to/retrieved from the lower byte of the device connected to the SRAM1 interface

• Byte 3 (i.e. SEL_I (3)) will be directed to/retrieved from the upper byte of the device connected to the SRAM1 interface.

For 16-bit SDRAM devices, the SDRAM_BE[1..0] signals are used by the Memory Controller to direct the relevant byte of data to/retrieve the relevant byte of data from, the appropriate byte-location at the specified address in memory:

• Byte 0 (i.e. SEL_I (0)) will be directed to/retrieved from the lower byte of the device connected to the SDRAM0 interface (SDRAM0_BE(0))

• Byte 1 (i.e. SEL_I (1)) will be directed to/retrieved from the upper byte of the device connected to the SDRAM0 interface (SDRAM0_BE(1))

• Byte 2 (i.e. SEL_I (2)) will be directed to/retrieved from the lower byte of the device connected to the SDRAM1 interface (SDRAM1_BE(0))

• Byte 3 (i.e. SEL_I (3)) will be directed to/retrieved from the upper byte of the device connected to the SDRAM1 interface (SDRAM1_BE(1)).

Methods of Connection

Physical memory is connected to the processor's External Memory interface. Use the following linked pages to explore the methods of connection, from a single physical memory device, through to a range of memory devices – accessed by single or multiple processors.