WB_LCDCTRL - Operational Overview

Frozen Content

Modified by Admin on Nov 6, 2013

The LCD Controller is implemented as a Finite State Machine, with a maximum operating frequency of 50 MHz.

The Cycle Counter is an internal 7-bit counter used to control transitions between certain states of the FSM.

Internally, the ADR_I input is connected directly to the LCD_RS output. Similarly, the LCD_DATA bus is connected directly to the DAT_O bus.

The LCD_E and ACK_O outputs are both Low by default.

The state of the LCD_RW output is dependent on the current Wishbone data cycle – High when reading and Low when writing.

Data sent by the processor and appearing at the Controller's DAT_I input will be directly channelled onto the LCD_DATA bus when performing a write operation.

State Machine Operation

The Controller's FSM has 6 states. The operation of the FSM can be summarized as follows and is particularly useful as it indicates the length of a complete read/write cycle and the minimum time between consecutive cycles:

State 1 (Address Setup) – this is the initial state for the Controller. The Controller resets the Cycle Counter to 0000000 in this state and will remain in this state until the host processor takes the STB_I and CYC_I lines High.

State 2 (Setup Delay 1) – this state simply provides a delay of one clock cycle (CLK_I)

State 3 (Setup Delay 2) – this state simply provides a delay of one clock cycle (CLK_I)

State 4 (Enable LCD) – in this state, the LCD_E output is taken High (thus enabling the LCD panel). The Controller remains in this state until the Cycle Counter reaches a count of 15 (300ns @ 50MHz)

State 5 (Acknowledge) – in this state, the Controller takes its ACK_O output High, signifying to the host processor that the requested task has been carried out. If performing a write operation, the LCD_E output will be taken Low at this time. If performing a read operation, the LCD_E output will remain High until the read is complete. The host will capture the data one cycle after the ACK_O signal is taken High. The Controller also resets the Cycle Counter to 0000000 in this state

State 6 (Post Acknowledge Delay) – this state simply provides a delay of 80 clock cycles (1600ns @ 50MHz), after which time the Controller enters the initial Address Setup state and a new read/write cycle can begin.