WB_JPGDEC_V2 - Accessible Internal Registers
Contents
- Status Register (STATUS)
- Interrupt Mask Register (INTMASK)
- Image Size Registers (SIZE_X, SIZE_Y)
- Decoding Area Registers (START_X, START_Y, END_X, END_Y)
- Read Address Register (READ_ADDR)
- Read Count Register (READ_COUNT)
- Write Start Address Register (WRITE_STARTADDR)
- Write End Address Register (WRITE_ENDADDR)
- Write Offset Register (WRITE_OFFSET)
- Write Width Register (WRITE_WIDTH)
- Write Address Register (WRITE_ADDR)
The following sections detail the internal registers for the WB_JPGDEC_V2 that can be accessed from the host processor.
Status Register (STATUS)
Address: 0h
Access: Read only except where indicated
Value after Reset: 0000_0100h
This register reflects the state of the WB_JPGDEC_V2 at all times.
MSB LSB | |||||||||
31 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | rst | start | unsup | corupt | notjpg | jpgerr | wfull | rempty | jpgrdy |
Bit | Symbol | Function |
---|---|---|
STATUS.31..STATUS.9 | - | Not Used. |
STATUS.8 (R/W) | rst | Reset bit. Writing a '1' to this bit issues a software reset – forcing the end of decoding and placing the WB_JPGDEC_V2 back into the idle state. As a result of setting this bit, the
This flag will remain set while the WB_JPGDEC_V2 is in the idle state. Cleared by writing '1' to |
STATUS.7 (W) | start | Start bit. Writing a '1' to this bit results in a software reset, followed by the start of decoding. The |
STATUS.6 (R) | unsup | Unsupported flag. This bit will be set if the format of the supplied JPEG image is not supported (i.e. is not a baseline JPEG). Cleared by writing '1' to |
STATUS.5 (R) | corupt | Corrupt flag. This bit will be set if an unknown error occurs while processing the JPEG image. Cleared by writing '1' to |
STATUS.4 (R) | notjpg | Not a JPEG flag. This bit will be set if the input is not marked as a JPEG image. Cleared by writing '1' to |
STATUS.3 (R) | jpgerr | JPEG Error flag. This bit will be set if any error occurs while processing the JPEG image (i.e. |
STATUS.2 (R/W) | wfull | Write Destination Full flag. This bit will be set if the output data is about to be written outside of the output address window specified by the values in the WRITE_STARTADDR and WRITE_ENDADDR registers.
If set, write to this bit with a '1' to clear it and resume decoding. |
STATUS.1 (R/W) | rempty | Read Buffer Empty flag. This bit will be set if the Read Buffer becomes empty and more data is needed.
If set, write to this bit with a '1' to clear it and resume decoding. |
STATUS.0 (R) | jpgrdy | JPEG Ready Flag. This bit will be set if the entire JPEG image has been correctly processed. Cleared by writing '1' to |
Values written to read-only bits in the register (unsup
, corupt
, notjpg
, jpgerr
and jpgrdy
) will be ignored. The write-only start
bit will return '0' when read.
Interrupt Mask Register (INTMASK)
Address: 1h
Access: Read and Write
Value after Reset: 0000_0000h
This register is used to enable interrupt generation for each of the readable bits in the Status register (STATUS.7, STATUS.6..0). Provided bit INTMASK.n is High, an interrupt will be generated when the corresponding bit STATUS.n goes High.
MSB LSB | |||||||||
31 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | rst | - | unsup | corupt | notjpg | jpgerr | wfull | rempty | jpgrdy |
Bit | Symbol | Function |
---|---|---|
INTMASK.31..INTMASK.9 | - | Not Used. |
INTMASK.8 | rst | Enables interrupt generation for the Reset flag (STATUS.8). |
INTMASK.7 | - | Not used. Values written to this bit will be ignored. Returns '0' when read. |
INTMASK.6 | unsup | Enables interrupt generation for the Unsupported flag (STATUS.6). |
INTMASK.5 | corupt | Enables interrupt generation for the Corrupt flag (STATUS.5). |
INTMASK.4 | notjpg | Enables interrupt generation for the Not a JPEG flag (STATUS.4). |
INTMASK.3 | jpgerr | Enables interrupt generation for the JPEG Error flag (STATUS.3). |
INTMASK.2 | wfull | Enables interrupt generation for the Write Destination Full flag (STATUS.2). |
INTMASK.1 | rempty | Enables interrupt generation for the Read Buffer Empty flag (STATUS.1). |
INTMASK.0 | jpgrdy | Enables interrupt generation for the JPEG Ready flag (STATUS.0). |
Image Size Registers (SIZE_X, SIZE_Y)
Address: 2h
and 3h
Access: Read only (from processor)
Value after Reset: 0000_0000h
These 32-bit registers are used to store 16-bit values for the width (SIZE_X) and height (SIZE_Y) of the image, in pixels, respectively. This information is obtained directly from the JPEG image itself.
The SIZE_X register always stores the actual width of the JPEG image, regardless of whether it is an odd or even number of pixels. However internally, the WB_JPGDEC_V2 ensures only even values for width are used. This is achieved using an additional internal register, SIZE_X_EVEN, loaded with bits 15..1 of the SIZE_X register, and '0' into its LSB. This register is not accessible by the processor.
Bits 31..16 of these registers are not used and will return '0' when read.
MSB LSB | |
31 16 | 15 0 |
- | size_x |
MSB LSB | ||
31 16 | 15 1 | 0 |
- | size_x_even | 0 |
MSB LSB | |
31 16 | 15 0 |
- | size_y |
Decoding Area Registers (START_X, START_Y, END_X, END_Y)
Address: 4h
, 5h
, 6h
, 7h
Access: Read and Write
Value after Reset: 0000_0000h
These 32-bit registers together define the area of the JPEG image that is to be decoded. The 16-bit values in the START_X and START_Y registers define the top-left corner of the decoding area. The 16-bit values in the END_X and END_Y registers define the bottom-right corner of the decoding area.
If a decode area is not explicitly defined, the entire image will be decoded, using the values for the width and height of the JPEG image (stored in the SIZE_X_EVEN and SIZE_Y registers respectively).
The top-left corner of the area will be the first pixel written to memory, at the address defined by the initial value stored in the Write Address register (WRITE_ADDR).
As two pixels are written to memory at the same time during decoding, the pixel boundary must be even and so START_X and END_X values must be multiples of 2. This is handled upon writing to these registers by truncating the value and ensuring that '0' is loaded into the LSB.
Bits 31..16 of these registers are not used and will return '0' when read.
MSB LSB | ||
31 16 | 15 1 | 0 |
- | start_x | 0 |
MSB LSB | |
31 16 | 15 0 |
- | start_y |
MSB LSB | ||
31 16 | 15 1 | 0 |
- | end_x | 0 |
MSB LSB | |
31 16 | 15 0 |
- | end_y |
Read Address Register (READ_ADDR)
Address: 8h
Access: Read and Write
Value after Reset: XXXX_XXXXh
This register is used to store the 32-bit address in memory from where the WB_JPGDEC_V2 will start reading the next data of the JPEG image.
While reading, the value in the READ_ADDR register will be incremented (ready to get the next byte of the image).
Read Count Register (READ_COUNT)
Address: 9h
Access: Read and Write
Value after Reset: 0000_0000h
This register is used to store a 32-bit value for the number of bytes that the WB_JPGDEC_V2 will read from the JPEG image, starting from the initial byte at the initial address loaded into the READ_ADDR register.
While reading, the value in the READ_COUNT register will be decremented. If READ_COUNT reaches zero and the JPEG is not yet fully decoded, the rempty
bit in the Status register (STATUS.1) will be set – flagging that no more data can be read. To resume decoding, the following must be performed:
- Write new values to the READ_ADDR and READ_COUNT registers
- Clear the
rempty
bit in the Status register. This is achieved by writing a '1' to this bit.
Write Start Address Register (WRITE_STARTADDR)
Address: Ah
Access: Read and Write
Value after Reset: 0000_0000h
This register is used to define a starting address in memory at which the resulting decoded image can be written. The value in this register defines the lower limit in memory that the WB_JPGDEC_V2 will write into, irrespective of the value specified in the WRITE_OFFSET register, or the size of the JPEG.
The address must be located at a 32-bit boundary and therefore the value stored for the start address must be a multiple of 4. Bits 1..0 are therefore always '0'.
MSB LSB | ||
31 2 | 1 | 0 |
write_start_address | 0 | 0 |
Write End Address Register (WRITE_ENDADDR)
Address: Bh
Access: Read and Write
Value after Reset: 0000_0000h
This register is used to define an end address in memory, up to which the resulting decoded image can be written. The value in this register defines the upper limit in memory that the WB_JPGDEC_V2 will write into, irrespective of the value specified in the WRITE_OFFSET register, or the size of the JPEG.
The address must be located at a 32-bit boundary and therefore the value stored for the end address must be a multiple of 4. Bits 1..0 are therefore always '0'.
MSB LSB | ||
31 2 | 1 | 0 |
write_end_address | 0 | 0 |
Write Offset Register (WRITE_OFFSET)
Address: Ch
Access: Read and Write
Value after Reset: 0000_0000h
This register is used to store an offset value, allowing you to shift where in memory the resulting decoded image will start to be written. The offset is relative to the value stored for the start address, in the WRITE_STARTADDR register.
The address must be located at a 32-bit boundary and therefore the value stored for the offset must be a multiple of 4. Bits 1..0 are therefore always '0'.
MSB LSB | ||
31 2 | 1 | 0 |
write_offset | 0 | 0 |
Write Width Register (WRITE_WIDTH)
Address: Dh
Access: Read and Write
Value after Reset: 0000_0000h
This register is used to store a 16-bit value for the required width of the decoded output image, in pixels. If the decoded JPEG image is being written directly to screen, the value for the screen line width, in pixels should be entered into this register. If the decoded image is being written as an image in continuous memory, this register should be left with the value of zero. In the latter case, the value stored for the width of the JPEG image – in the SIZE_X_EVEN register – will be used instead.
How the value in the WRITE_WIDTH register is used, depends on the width of the original JPEG image being decoded:
- If the JPEG is smaller in width than the required width, pixels will be skipped during decoding.
- If the JPEG is greater in width than the required width, pixels will be discarded during decoding.
If the value in the WRITE_WIDTH register is zero, then all pixels of image lines will be written to memory, with no gaps between lines.
As two pixels are written to memory at the same time during decoding, the pixel boundary must be even and so the value in the WRITE_WIDTH register must be a multiple of 2. This is handled upon writing to the register by truncating the value and ensuring that '0' is loaded into the LSB.
Bits 31..16 of this register are not used and will return '0' when read.
MSB LSB | ||
31 16 | 15 1 | 0 |
- | write_width | 0 |
Write Address Register (WRITE_ADDR)
Address: Eh
Access: Read only
Value after Reset: 0000_0000h
This register is used to contain the address in memory at which the WB_JPGDEC_V2 will write the next pixel of the decoded image.
The actual address for a write must be located at a 32-bit boundary and therefore the value stored for the address must be a multiple of 4. Bits 1..0 are therefore always '0'.
The actual address of an RGB565 formatted pixel (X, Y) written by the WB_JPGDEC_V2 can be summarized by the expression:
write_addr = write_startaddr - write_offset + ((X + (write_width * Y)) * 2)
where:
write_addr
is the value stored in the WRITE_ADDR register
write_startaddr
is the value stored in the WRITE_STARTADDR register
write_offset
is the value stored in the WRITE_OFFSET register
write_width
is the value stored in the WRITE_WIDTH register. Note that if the value in this register is zero, thensize_x_even
, the value in the SIZE_X_EVEN register will be used instead.
If the WB_JPGDEC_V2 tries to write a pixel while the value stored in the WRITE_ADDR register is outside of the target memory address window – defined by the values in the WRITE_STARTADDR and WRITE_ENDADDR registers – the wfull
bit in the Status register (STATUS.2) will be set and decoding of the JPEG image will be suspended. To resume decoding, perform the following:
- Write new values to at least one of the following registers: WRITE_STARTADDR, WRITE_ENDADDR, WRITE_OFFSET
- Clear the
wfull
bit in the Status register. This is achieved by writing a '1' to this bit.
MSB LSB | ||
31 2 | 1 | 0 |
write_addr | 0 | 0 |