WB_INTERCON - Pin Description
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Table 1 summarizes the function of each of the pins available for the WB_INTERCON. Only the pins for one slave interface are listed. The function of each of the pins of subsequently added slave interfaces is identical – only the pin names change with respect to their prefix (i.e. s0 for slave interface 0, s1 for slave interface 1, and so on).
Table 1. WB_INTERCON Pin description.| Name | Type | Polarity/ Bus size | Description |
|---|---|---|---|
| Wishbone Master Interface Signals | |||
| m0_STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| mo_CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| m0_ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes High, the connected Wishbone slave device has finished execution of the requested action and the current bus cycle is terminated |
| m0_ADR_I | I | 24/32 (see note 1) | Standard Wishbone address bus. The address provided on this bus is decoded to select the correct slave device that the processor wishes to communicate with and also which memory address/internal register of that device is accessed |
| m0_DAT_O | O | 32 | Data to be sent to the connected Wishbone master device |
| m0_DAT_I | I | 32 | Data received from the connected Wishbone master device |
| m0_SEL_I | I | 4/High | Select input, used to determine where data is placed on the m0_DAT_O line during a Read cycle and from where on the m0_DAT_I line data is accessed during a Write cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| m0_WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle. 0 = Read |
| m0_CLK_I | I | Rise | External (system) clock signal |
| m0_RST_I | I | High | External (system) reset signal |
| Wishbone Slave Interface Signals | |||
| s0_STB_O | O | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| s0_CYC_O | O | High | Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| s0_ACK_I | I | High | Standard Wishbone device acknowledgement signal. When this signal goes High, the connected Wishbone slave device has finished execution of the requested action and the current bus cycle is terminated |
| s0_ADR_O | O | 0-32 (see note 2) | Standard Wishbone address bus. When the WB_INTERCON is used to connect to one or more slave memory devices, this bus is used to select an address in the connected memory device for writing to/reading from. When the WB_INTERCON is used to connect to one or more slave peripheral devices, this bus is used to select an internal register in the connected peripheral device for writing to/reading from. |
| s0_DAT_I | I | 8/16/32 (see note 3) | Data received from the connected Wishbone slave device |
| s0_DAT_O | O | 8/16/32 (see note 3) | Data to be sent to the connected Wishbone slave device |
| s0_SEL_O | O | 4/High | Select output, used to determine where data is placed on the s0_DAT_O line during a Write cycle and from where on the s0_DAT_I line data is accessed during a Read cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| s0_WE_O | O | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle. 0 = Read |
| s0_CLK_O | O | Rise | External (system) clock signal (identical to m0_CLK_I), made available for connecting to the CLK_I input of the connected slave device. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design |
| s0_RST_O | O | High | Reset signal made available for connection to the RST_I input of the connected slave device. This signal goes High when an external reset is issued to the unit on its m0_RST_I pin. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design |
| Interrupt Signals (Multiplexed Peripheral I/O Devices only) | |||
| m0_INT_O | O | 32 | Interrupt signals sent to the connected Wishbone master device |
| sn_INT_I | I | p (see note 4) | The number of interrupt input signals (p) received from the associated slave peripheral device (where n represents the particular slave interface) |
| Spare_INT_I | I | 32 - q (see note 5) | Spare interrupt signals input. If the connected slave peripheral devices do not use all 32 individual interrupt signals that can be passed to the processor, those remaining can be made available to receive interrupt signals from other circuitry in the design |
Notes
- m0_ADR_I will be 24 bits when connected to the processor's Peripheral I/O interface and 32 bits when connected to the External Memory interface. Use the Master Address Size option when configuring the Interconnect device to define this address bus sizing.
- The number of address bits is determined by the value entered for the Address Bus Width, when defining the properties for a slave device.
- The size of the data bus is determined by the value entered for the Data Bus Width, when defining the properties for a slave device.
- This number is determined by the value entered for the Used Interrupts, when defining the properties for a slave device.
- Where q represents the total number of interrupt pins assigned to all connected slave devices.