WB_INTERCON - Interfacing
Contents
The WB_INTERCON component can be used to connect to one or more slave memory or peripheral I/O devices. The following sections provide examples of where the interconnect component can be used in a design.
Connecting Single Slave Devices
Although a single memory or peripheral I/O device can be connected directly to the respective Wishbone interface of a processor (with additional wiring), use of a Wishbone Interconnect component greatly simplifies matters, not only from its ease of physical connection on the schematic, but also from its ability to handle the address mapping from the processor to the slave device.
Figure 1 shows the use of a Wishbone Interconnect component to connect the SRAM on a daughter board to the External Memory interface of a TSK3000A processor. The physical SRAM is connected to the interconnect via an appropriately-configured Memory Controller component (WB_MEM_CTRL).
Figure 1. Using a Wishbone Interconnect component to facilitate simple connection to memory.
Figure 2 shows similar use of a Wishbone Interconnect component to connect a single slave peripheral device (a VGA Controller) to a TSK3000A's Peripheral I/O interface.
Figure 2. Using a Wishbone Interconnect component to facilitate simple connection to a single slave peripheral.
Connecting Multiple Memory Devices
The nature of your design may warrant the use of several memory devices, possibly of differing type, each of which requires to be mapped into a specific location within the processor's address space. This can be readily achieved through the use of a Wishbone Interconnect component. Simply connect the Wishbone Master interface of the WB_INTERCON directly to the processor's External Memory Interface and then add and configure interfaces to each slave memory device as required.
Figure 3 illustrates the use of a Wishbone Interconnect component to connect to various external static RAM devices and a dedicated single-port block of RAM within the design. In each case, the respective Memory Controller (configured as either an SRAM Controller or a BRAM Controller) sits between the Wishbone Interconnect component and the physical memory device(s).
Figure 3. Multiplexing a 32-bit processor's External Memory interface using a Wishbone Interconnect component.
Connecting Multiple Peripheral I/O Devices
Typically in a design, the processor will need to interface to multiple Wishbone-compliant peripherals. Each of these peripherals may contain any number of internal registers with which to write to/read from. It is not possible to communicate directly, and simultaneously, with each of these slave devices. A means of multiplexing must be used, allowing the processor to talk to any number of slaves over the one interface.
Again, this can be readily achieved through the use of a Wishbone Interconnect component. Simply connect the Wishbone Master interface of the WB_INTERCON directly to the processor's Peripheral I/O Interface and then add and configure interfaces to each slave peripheral device as required.
In the example circuit of Figure 4, the Wishbone Interconnect component enables a single 32-bit processor (TSK3000A) to communicate with three Wishbone-compliant peripheral devices (a 1X8 Parallel Port Unit, a Serial Port Unit and a PS2 Controller).
Figure 4. Multiplexing the TSK3000A's peripheral I/O interface using a Wishbone Interconnect component.
Dual-Mastering
Some designs may require shared access to one or more slave memory or peripheral devices. This can be achieved by using both a configurable Wishbone Dual Master component (WB_DUALMASTER) and a configurable Wishbone Interconnect component (WB_INTERCON).
This makes it possible to connect two processor masters to a whole bank of slave memory or peripheral devices. The devices would be mapped into the respective processor address spaces at identical locations. Figure 5 shows an example of using both a Wishbone Dual Master component and a Wishbone Interconnect component to allow two TSK3000A processors to access a variety of physical slave memory devices.
Figure 5. Sharing multiple slave memory devices between two processors.
Figure 6 shows an example of using both a Wishbone Dual Master component and a Wishbone Interconnect component to allow two TSK3000A processors to access three different slave peripheral devices (two parallel port units and an Ethernet Media Access Controller).
Figure 6. Sharing multiple slave peripheral devices between two processors.
Sharing Peripheral Devices
Although the Wishbone Dual Master component can be used to share peripheral devices between two processors, it cannot provide marshalling for interrupts from the peripherals through to those processors. If the peripheral devices being shared do not generate interrupts, or they are not being used, then use of a Wishbone Dual Master – in series with a Wishbone Interconnect – is fine. In Figure 6 (previous), the port units do not generate interrupts and the interrupt from the EMAC is not being used.
If you need to share peripherals between processors, then you should consider using a Wishbone Multi-Master component. It can be configured to have between two and eight masters but, more importantly, it can pass interrupts from a connected Wishbone Interconnect through to all connected 32-bit processors. This makes it ideal for use on the peripheral side, when multiple 32-bit processors require shared access to a block of peripheral devices, and one or more of those devices generate interrupts.
Figure 7. Sharing peripheral devices between processors using a Wishbone Multi-Master.