WB_IDE - Host to Controller Communications
Communications between a 32-bit host processor and the WB_IDE Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.
Table 1 summarizes how the 32-bit data word from the host processor is used by each of the internal registers.
Table 1. Values written to internal registers during a write.| Writing to... | Results in... |
|---|---|
DATA | DAT_I(15..0) loaded into bits 15..0 of the Data register |
COMMAND | DAT_I(7..0) loaded into the Command register |
MEMSTART | DAT_I(31..2) and "00" loaded into the Memory DMA Start Address register |
SETUP | DAT_I(15..0) loaded into the Setup register |
Table 2 summarizes the 'make-up' of the 32-bit data word that is read back from each register.
Table 2. Values read from internal registers during a read.| Reading from... | Presents (to host processor)... |
|---|---|
DATA | "00000000000000" & 18-bit value from the Data register |
MEMSTART | 32-bit value from the Memory DMA Start Address register |
SETUP | "0000000000000000" & 16-bit value from the Setup register |